Sensitivity guided net weighting for placement-driven synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 5, 2005, Pages 711-720

  Ren, Haoxing ^a   Pan, David Z ^b   Kung, David S ^c  

^a IBM   (United States)

^b The University of Texas at Austin   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Interconnect; Net weighting; Physical synthesis; Sensitivity analysis; Timing driven placement (TDP)

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; OPTICAL INTERCONNECTS; OPTIMIZATION; SENSITIVITY ANALYSIS;

INTERCONNECTS; NET WEIGHTING; PHYSICAL SYNTHESIS; TIMING-DRIVEN PLACEMENT (TDP);

VLSI CIRCUITS;

EID: 18744384123     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.846367     Document Type: Article

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