Parameter variation tolerance and error resiliency: New design paradigm for the nanoscale era

Proceedings of the IEEE

Volumn 98, Issue 10, 2010, Pages 1718-1751

  Ghosh, Swaroop ^a   Roy, Kaushik ^b  

^a INTEL CORPORATION   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

Digital signal processing; graceful quality degradation; low power; process variations; process tolerant design; reliability; robust design; voltage scaling

Indexed keywords

DEGRADATION; DIGITAL SIGNAL PROCESSING; INTEGRATED CIRCUIT DESIGN; RELIABILITY; VOLTAGE SCALING;

LOW POWER; PROCESS TOLERANT; PROCESS VARIATION; QUALITY DEGRADATION; ROBUST DESIGNS;

COMPUTER CIRCUITS;

EID: 77957012605     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2010.2057230     Document Type: Article

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