A probabilistic framework to estimate full-chip subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations

Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04

Volumn , Issue , 2004, Pages 156-161

  Zhang, Songqing ^a   Wason, Vineet ^a   Banerjee, Kaustav ^a  

^a University of California   (United States)

Author keywords

Die to die variations; Electrothermal couplings; Process variations; Subthreshold leakage power distribution; Within die variations; Yield estimation

Indexed keywords

DIE-TO-DIE VARIATIONS; ELECTROTHERMAL COUPLINGS; PROCESS VARIATIONS; SUBTHRESHOLD LEAKAGE POWER DISTRIBUTION; WITHIN-DIE VARIATIONS; YIELD ESTIMATION;

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ESTIMATION; MICROPROCESSOR CHIPS; PROBABILITY; STATISTICAL METHODS;

LEAKAGE CURRENTS;

EID: 16244421701     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

1. S. Borkar, T. Kamik, S. Narendra, J. Tschanz, A. Keshavarzi, V. De, "Parameter variations and impact on circuits and microarchitecture," DAC, 2003, pp. 338-342.
2. S. Borkar, "Design challenges of technology scaling," IEEE Micro, vol. 19, pp. 23-29, Jul-Aug 1999.
3. K. A. Bowman, S. G. Duvall, and J. D. Meindl, "Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration," IEEE J. Solid-State Circuits, vol. 37, pp. 183-190, Feb. 2002.
4. H. Su, F. Liu, A. Devgan, E. Acar, and S. Nassif, "Full chip leakage estimation considering power supply and temperature variations," ISLPED, 2003, pp. 78-83.
5. R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester, "Statistical analysis of subthreshold leakage current for VLSI Circuits," IEEE Trans. on VLSI Systems, vol. 12, no.2, pp. 131-139, 2004.
6. S. Mukhopadhyay and K. Roy, "Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation," ISLPED, 2003, pp. 172-175.
7. S. Narendra, V. De, S. Borkar, D. Antoniadis and A. Chandrakasan, "Full-chip sub-threshold leakage power prediction model for sub-0.18μm CMOS," ISLPED, 2002, pp. 19-23.
8. Srivastava, R. Bai, D. Blaauw and D. Sylvester, "Modeling and analysis of leakage power considering within-die process variations," ISLPED, 2002, pp. 64-67.
9. Y. S. Lin, C. C. Wu, C. S. Chang, R. P. Yang, W. M. Chen, J. J. Liaw, and C. H. Diaz, "Leakage scaling in deep submicron CMOS for SoC," IEEE Trans. Electron Devices, vol. 49, pp. 1034-1041, Jun. 2002.
10. Intl. Technology. Roadmap for Semiconductors (ITRS): 2003:http://public.itrs.net/
11. K. Roy, S. Mukhopadhyay, H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits," Proc. of the IEEE, vol. 91, no. 2, pp. 305-327, Feb, 2003.
12. S. Mukhopadhyay, A. Raychowdhury, and K. Roy, "Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling," DAC, 2003, pp. 169-174.
13. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge Univ. Press, 1998.
14. K. Banerjee, S. C. Lin, A. Keshavarzi, S. Narendra, and V. De, "A self-consistent junction temperature estimation methodology for nanometer scale ICs with implications for performance and thermal management", IEDM, 2003, pp. 887-890.
15. J. Zhang and M. Styblinski, Yield and Variability Optimisation of Integrated Circuits, Kluwer Academic Publishers, Boston, 1995.
16. BSIM3 manual:http://www-device.eecs.berkeley.edu/~bsim3/ftpv323/Mod_doc/ BSIM3v323_manu.tar
17. http://www-device.eecs.berkeley.edu/~ptm/mosfet.html