Analytical modeling of SRAM dynamic stability

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2006, Pages 315-322

  Zhang, Bin ^a   Arapostathis, Ari ^a   Nassif, Sani ^b   Orshansky, Michael ^a  

^a The University of Texas at Austin   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

(E ,2E) THEORY; ANALYTICAL MODELING; ANALYTICAL PREDICTIONS; BI STABLE; CLOSED-FORM EXPRESSIONS; COMPUTER-AIDED DESIGN; DYNAMIC NOISE; DYNAMIC STABILITY; INTERNATIONAL CONFERENCES; NOISE SIGNALS; QUANTITATIVE RESULT; SPECIFIC CHARACTERISTICS; SPICE SIMULATIONS; SRAM CELLS; TRANSIENT ERRORS; TRANSIENT NOISE;

DESIGN; FEEDBACK; FORECASTING; NEURAL NETWORKS; NONLINEAR SYSTEMS; SPICE; STATE FEEDBACK; STATIC RANDOM ACCESS STORAGE;

CELLS;

EID: 46149119897     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320052     Document Type: Conference Paper

References (19)

1. E. Seevinck, F. J. List and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells," JSSC, 1987, pp. 748-754.
2. J. Lohstroh, E. Seevinck and J. D. Groot, "Worst-case static noise margin criteria for logic circuits and their mathematical equivalence," JSSC, 1983, pp. 803-807.
3. H. H. Chen and J. S. Neely, "Interconnect and circuit modeling techniques for full-chip power supply noise analysis," IEEE Trans. Components, Packaging, and Manufacturing Technology-Fart B, 1998, pp. 209-215.
4. R. Gharpurey and R. G. Meyer, "Modeling and analysis of substrate coupling in IC's," IEEE Custom-Integrated Circuit Conf., 1995, pp. 125-128.
5. H.-R. Cha and O.-K. Kwon, "An analytical model of simultaneous switching noise in CMOS systems," IEEE Trans. Advanced Packaging, 2000, pp. 62-68.
6. P. E. Dodd and L. W. Massengill, "Basic mechanisms and modeling of single-event upset in digital microelectronics," IEEE Trans. Nucl. Sci., 2003, pp. 583-602.
7. D. C. Pham, et. al., "Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor," JSSC, 2006, pp. 179-196.
8. J. S. Fu, C. L. Axness and H. T. Weaver, "Two-dimensional simulation of single event induced bipolar current in CMOS structures," IEEE Trans. Nucl. Sci., 1984, pp. 1155-1159.
9. P. Hazucha and C. S vensson, "Impact of CMOS technology scaling on the atmospheric neutron soft error rate," IEEE Trans. Nucl. Sci., 2000, pp. 2586-2594.
10. K. Mayaram, J.-H. Chern and P. Yang, "Algorithms for transient three-dimensional mixed-level circuit and device simulation," IEEE Trans. Computer-Aided Design, 1993, pp. 1726-1733.
11. K. Mohanram, "Closed-form simulation and robustness models for SEU-tolerant design," VLSI Test Symp., 2005, pp. 327-333.
12. A. Dharchoudhury, et al., "Fast timing simulation of transient faults in digital circuits," ICCAD, 1994, pp. 719-726.
13. M. Omana, et al., "A model for transient fault propagation in combinatorial logic," Intl. On-line Testing Symp., 2003, pp. 111-115.
14. R. Heald and P. Wang, "Variability in sub-100nm SRAM designs," ICCAD, 2004, pp. 347-352.
15. M. Horowitz, "Timing models for MOS circuits," Ph. D. Dissertation, Stanford University, 1984.
16. Z. Vukic, et. al., Nonlinear Control Systems, Marcel Dekker Inc., 2003.
17. N. Fiedenstierna and K. O. Jeppson, " CMOS circuit speed and buffer optimization, " IEEE Trans. Computer-Aided Design, 1987, pp. 270-281.
18. T. Sakurai and A. R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter," JSSC, 1990, pp. 584-594.
19. PTM, http://www.eas.asu.edu/-ptm/.