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Volumn 2005, Issue , 2005, Pages 659-662

Fluctuation limits & scaling opportunities for CMOS SRAM cells

Author keywords

[No Author keywords available]

Indexed keywords

CELL STORAGE; CELL TERMINAL VOLTAGES; VOLTAGE DEPENDENCIES;

EID: 33847721007     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (146)

References (14)
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  • 4
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    • P. A. Stolk et al, "CMOS device optimization for mixed-signal technologies", IEDM Tech. Dig., pp. 215-218, Dec 2001.
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  • 5
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  • 6
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    • Shuji Ikeda, Technology for High-Density and High-Performance SRAM', Chap. 5, Ph.D. Dissertation, Tokyo Inst. of Tech., Oct 2003.
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  • 7
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    • Apr 01
    • A. Bhavnagarwala et al, "Impact of Intrinsic Fluctuations on CMOS SRAM Cell Stability", IEEE JSSC, Vol 36, No. 4, pp. 658-665, Apr 01.
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    • Bhavnagarwala, A.1
  • 8
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    • A Study of the threshold voltage variation for ultra-small bulk and SOI CMOS
    • Sep
    • K. Takeuchi et al, "A Study of the threshold voltage variation for ultra-small bulk and SOI CMOS" IEEE TED. Vol. 48, No. 9, Sep 2001, pp. 1995-2001.
    • (2001) IEEE TED , vol.48 , Issue.9 , pp. 1995-2001
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  • 10
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  • 13
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  • 14
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.