A 1.1GHz 12μA/Mb-leakage SRAM design in 65nm ultra-low-power CMOS with integrated leakage reduction for mobile applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 324-326

  Wang, Y ^a   Ahn, H ^a   Bhattacharya, U ^a   Coan, T ^a   Hamzaoglu, F ^a   Hafez, W ^a   Jan, C H ^a   Kolar, P ^a   Kulkarni, S ^a   Lin, J ^a   Ng, Y ^a   Post, I ^a   Wei, L ^a   Zhang, Y ^a   Zhang, K ^a   Bohr, M ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; ELECTRIC POTENTIAL; MOBILE TELECOMMUNICATION SYSTEMS; STATIC RANDOM ACCESS STORAGE;

INTEGRATED LEAKAGE; MEMORY CELL; RETENTION VOLTAGE; SUPPLY VOLTAGE;

CMOS INTEGRATED CIRCUITS;

EID: 34548825093     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373425     Document Type: Conference Paper

References (6)

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2. M. Yamaoka, N. Maeda, Y Shinozaki, et al., "Low-Power Embedded SRAM Modules with Expanded Margins for Writing," ISSCC Dig. Tech. Papers, pp. 480-481, Feb., 2005.
3. Y. Takeyama, H. Otake, O. Hirabayashi, et al., "A Low Leakage SRAM Macro with Replica Cell Biasing Scheme," Symp. VLSI Circuits, pp. 166-167, Jun., 2005.
4. T. Suzuki, Y. Yamagami, I. Hatanaka, et al., "A Sub-0.5-V Operating Embedded SRAM Featuring a Multi-Bit-Error-Immune Hidden-ECC Scheme," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 152-160, Jan., 2006.
5. C.-H. Jan, P. Bai, J. Choi, et al., "A 65nm Ultra Low Power Logic Platform Technology Using Uni-axial Strained Silicon Transistors," IEDM Tech. Dig., pp. 65-66, Dec., 2005.
6. K. Zhang, U. Bhattacharya, Z. Chen, et al., "SRAM Design on 65-nm CMOS Technology with Dynamic Sleep Transistor for Leakage Reduction," IEEE J. Solid-State Circuits, pp. 895-901, Apr., 2005.