Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization [logic IC design]

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2003-January, Issue , 2003, Pages 158-163

  Nguyen, D ^a   Davare, A ^a   Orshansky, M ^a   Chinnery, D ^a   Thompson, B ^a   Keutzer, K ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Circuits; Delay; Design optimization; Energy consumption; Libraries; Linear programming; Logic design; Logic programming; Minimization methods; Threshold voltage

Indexed keywords

ALGORITHMS; DELAY CIRCUITS; DESIGN; ELECTRIC POWER UTILIZATION; ENERGY UTILIZATION; GATES (TRANSISTOR); INTEGRATED CIRCUIT DESIGN; LEAKAGE CURRENTS; LIBRARIES; LINEAR PROGRAMMING; LOGIC DESIGN; LOGIC PROGRAMMING; LOW POWER ELECTRONICS; NETWORKS (CIRCUITS); OPTIMIZATION; POWER ELECTRONICS; THRESHOLD VOLTAGE;

DELAY; DESIGN OPTIMIZATION; DUAL SUPPLY VOLTAGES; DUAL THRESHOLD VOLTAGE; MINIMIZATION METHODS; OPTIMIZATION STRATEGY; SIZING OPTIMIZATION; TOTAL POWER CONSUMPTION;

LOGIC CIRCUITS;

EID: 1542359159     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231853     Document Type: Conference Paper

References (12)

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