Razor II: In situ error detection and correction for PVT and SER tolerance

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 400-622

  Blaauw, David ^a   Kalaiselvan, Sudherssen ^b   Lai, Kevin ^a   Ma, Wei Hsiang ^a   Pant, Sanjay ^a   Tokunaga, Carlos ^a   Das, Shidhartha ^c   Bull, David ^c  

^a UNIVERSITY OF MICHIGAN   (United States)

^b ADVANCED MICRO DEVICES   (United States)

^c ARM LTD   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

NETWORKS (CIRCUITS); SOLID STATE DEVICES;

ADAPTIVE METHODS; ENVIRONMENTAL CHANGE; ERROR DETECTION AND CORRECTION; IN-SITU DETECTIONS; LOWER-POWER CONSUMPTION; PVT VARIATIONS; RADIATION EXPERIMENT; SAFETY MARGIN;

VOLTAGE SCALING;

EID: 49549105128     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523226     Document Type: Conference Paper

References (5)

1. A. Drake, R. Senger, H. Deogun et al., "A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor," ISSCC Dig. Tech. Papers, Feb. 2007.
2. T. Burd, T. Pering, A. Stratakos, R. Brodersen, "A Dynamic Voltage Scaled Microprocessor System," IEEE J. Solid-State Circuits, vol. 35, no. 11, Nov. 2000.
3. M. Nakai, S. Akui, K. Seno et al., "Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor," IEEE J. Solid-State Circuits, vol. 40, no. 1, Jan. 2005.
4. K. Nowka, G. Carpenter, E. MacDonald et al., "A 32-bit PowerPC System-on-a-chip With Support for Dynamic Voltage Scaling and Dynamic Frequency Scaling," IEEE J. Solid-State Circuits, vol. 37, no. 11, Nov. 2002.
5. S. Das, D. Roberts, S. Lee, S. Pant et al., "A Self-Tuning DVS Processor Using Delay-Error Detection and Correction," IEEE J. Solid-State Circuits,vol. 41, no. 4, Apr. 2006.