An integrated modeling paradigm of circuit reliability for 65nm CMOS technology

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2007, Pages 511-514

  Wang, Wenping ^a   Reddy, Vijay ^b   Krishnan, Anand T ^b   Vattikonda, Rakesh ^a   Krishnan, Srikanth ^b   Cao, Yu ^a  

^a Arizona State University   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIAS CURRENTS; COMPUTER SIMULATION; LEAKAGE CURRENTS; MATHEMATICAL MODELS; PARAMETER ESTIMATION; RELIABILITY;

CIRCUIT PERFORMANCE; CIRCUIT RELIABILITY; PERFORMANCE DEGRADATION;

CMOS INTEGRATED CIRCUITS;

EID: 39549085217     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405783     Document Type: Conference Paper

References (13)

1. M. A. Alam and S. Mahapatra. A comprehensive model of PMOS NBTI degradation. Microelectronics Reliability, 45:71-81, Aug. 2005.
2. S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, and S. Vrudhula. Predictive modeling of the nbti effect for reliable design. CICC, pages 189-192, Sep. 2006.
3. A. Chatterjee, J. Yoon, S. Zhao, S. Tang, and Sadra K. et al. A 65nm cmos technology for mobile and digital signal processing applications. IEDM, pages 665-668, 2004.
4. K.-L. Chen, S. A. Saller, I. A. Groves, and D. B. Scott. Reliability effects on mos transistors due to hot-carrier injection. TED, 32(2):386-393, Feb. 1985.
5. C. Hu, S. C. Tarn, F.-C. Hsu, P.-K. Ko, T.-Y. Chan, and K. W. Terrill. Hot-electron-induced mosfet degradation - model, monitor, and improvement. TED, 32(2):375-385, Feb. 1985.
6. D. A. Johns and K. Martin. Analog integrated design, John Wiley, Sons Inc. 2004.
7. A. T. Krishnan, C. Chancellor, S. Chakravarthi, P. E. Nicollian, V. Reddy, and A. Varghese. Material dependence of hydrogen diffusion: Implication for nbti degradation. IEDM, Dec. 2005.
8. d, degradation of nmosfet's due to interface state generation by hot carrier injection. TED, 41(6):964-969, Jun. 1994.
9. S. Mahapatra, D. Saha, D. Varghese, and P B. Kumar. On the generation and recovery of interface traps in mosfets subjected to nbti, fn, and hci stress. TED, 53(7):1583-1592, Jul. 2006.
10. J. W. McPherson. Modeling and minimization of pmos nbti effect for robust nanometer design. DAC, pages 176-181, Jul. 2006.
11. V. Reddy, A. T. Krishnan, A. Marshall, J. Rodriguez, S. Natarajan, T Rost, and S. Krishnan. Impact of negative bias temperature instability on digital circuit reliability. IRPS, pages 248-254, Apr. 2002.
12. D. K. Schroder and J. A. Babcock. Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing. Journal of Applied Physics, 94(1):1-18, Jul. 2003.
13. R. Vattikonda, W. Wang, and Y. Cao. Modeling and minimization of pmos nbti effect for robust nanometer design. DAC, pages 1047-1052, Jul. 2006.