Novel sizing algorithm for yield improvement under process variation in nanometer technology

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 454-459

  Choi, Seung Hoon ^a   Paul, Bipul C ^b   Roy, Kaushik ^b  

^a INTEL CORPORATION   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

Algorithms; Design; Performance; Reliability

Indexed keywords

ALGORITHMS; DELAY CIRCUITS; NANOTECHNOLOGY; NONLINEAR PROGRAMMING; PARAMETER ESTIMATION; PROBABILITY; STATISTICAL METHODS;

PERFORMANCE ANALYSIS; PERFORMANCE DESIGN; SIZING ALGORITHMS;

PROCESS CONTROL;

EID: 4444264520     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996695     Document Type: Conference Paper

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