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Volumn , Issue , 2004, Pages 442-447

Parametric yield estimation considering leakage variability

Author keywords

Leakage; Parametric yield; Variability

Indexed keywords

CORRELATION METHODS; DELAY CIRCUITS; INVERSE PROBLEMS; MICROPROCESSOR CHIPS; NATURAL FREQUENCIES; PARAMETER ESTIMATION; RANDOM PROCESSES;

EID: 4444351567     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996693     Document Type: Conference Paper
Times cited : (114)

References (14)
  • 1
    • 33750599396 scopus 로고    scopus 로고
    • Leakage issues in IC design: Trends, estimation and avoidance
    • S. Narendra, D. Blaauw, A. Devgan and F. Najm, "Leakage issues in IC design: Trends, estimation and avoidance", Tutorial, ICCAD 2003.
    • (2003) ICCAD
    • Narendra, S.1    Blaauw, D.2    Devgan, A.3    Najm, F.4
  • 2
    • 0032592096 scopus 로고    scopus 로고
    • Design challenges of technology scaling
    • Jul
    • S. Borkar, "Design challenges of technology scaling", IEEE Micro, 19(4), pp. 23-29, Jul 1999.
    • (1999) IEEE Micro , vol.19 , Issue.4 , pp. 23-29
    • Borkar, S.1
  • 3
    • 1542329235 scopus 로고    scopus 로고
    • Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation
    • S. Mukhopadhyay, K. Roy, "Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation", ISLPED 2003.
    • (2003) ISLPED
    • Mukhopadhyay, S.1    Roy, K.2
  • 4
    • 84862407801 scopus 로고    scopus 로고
    • http://www-device.eecs.berkeley.edu/~ptm/
  • 7
    • 0042090415 scopus 로고    scopus 로고
    • Accurate estimate of total leakage current in scaled CMOS circuits based on compact current modeling
    • S. Mukhopadhyay, A. Raychowdhury, K. Roy, "Accurate estimate of total leakage current in scaled CMOS circuits based on compact current modeling", DAC 2003.
    • (2003) DAC
    • Mukhopadhyay, S.1    Raychowdhury, A.2    Roy, K.3
  • 8
    • 1542269365 scopus 로고    scopus 로고
    • Statistical estimation of leakage current considering inter- And intra-die process variation
    • R. Rao, A. Srivastava, D. Blaauw, D. Sylvester, "Statistical estimation of leakage current considering inter- and intra-die process variation", ISLPED 2003.
    • (2003) ISLPED
    • Rao, R.1    Srivastava, A.2    Blaauw, D.3    Sylvester, D.4
  • 9
    • 0036954781 scopus 로고    scopus 로고
    • Modeling and analysis of leakage power considering within-die process variations
    • A. Srivastava, R. Bai, D. Blaauw, D. Sylvester, "Modeling and analysis of leakage power considering within-die process variations", ISLPED 2002.
    • (2002) ISLPED
    • Srivastava, A.1    Bai, R.2    Blaauw, D.3    Sylvester, D.4
  • 10
    • 84862407800 scopus 로고    scopus 로고
    • http://www-device.eecs.berkeley.edu/~bsim3/bsim4.html
  • 12
    • 0142135003 scopus 로고    scopus 로고
    • Speed binning with path delay test in 150-nm technology
    • Oct
    • B. Cory, R. Kapur, B. Underwood, "Speed binning with path delay test in 150-nm technology", IEEE Design and Test of Computers, 20(5), pp. 45-45, Oct 2003
    • (2003) IEEE Design and Test of Computers , vol.20 , Issue.5 , pp. 45-45
    • Cory, B.1    Kapur, R.2    Underwood, B.3
  • 14
    • 0041633857 scopus 로고    scopus 로고
    • Computation and refinement of statistical bounds on circuit delay
    • A. Agarwal, D. Blaauw, V. Zolotov, S. Vrudhula, "Computation and refinement of statistical bounds on circuit delay", DAC 2003.
    • (2003) DAC
    • Agarwal, A.1    Blaauw, D.2    Zolotov, V.3    Vrudhula, S.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.