Efficient transistor-level sizing technique under temporal performance degradation due to NBTI

IEEE International Conference on Computer Design, ICCD 2006

Volumn , Issue , 2006, Pages 216-221

  Kang, Kunhyuk ^a   Kufluoglu, Haldun ^a   Alam, Muhammad Ashraful ^a   Roy, Kaushik ^a  

^a Purdue University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEGRADATION; ELECTRIC NETWORK ANALYSIS; FIELD EFFECT TRANSISTORS; LOGIC DEVICES; NEGATIVE TEMPERATURE COEFFICIENT; NETWORKS (CIRCUITS); SULFATE MINERALS; TIMING CIRCUITS; VLSI CIRCUITS;

AREA OVERHEAD; CIRCUIT DELAYS; CIRCUIT PERFORMANCES; CMOS LOGIC GATES; COMPUTER DESIGNS; INTERNATIONAL CONFERENCES; LIFETIME RELIABILITY; MODIFIED LAGRANGIAN; NANO SCALING; NBTI DEGRADATION; NEGATIVE BIAS- TEMPERATURE-INSTABILITY; OPERATION TIME; PERFORMANCE DEGRADATION; WORST-CASE SCENARIO;

THERMODYNAMIC STABILITY;

EID: 36949009341     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2006.4380820     Document Type: Conference Paper

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