Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 12, 2005, Pages 1859-1879

  Mukhopadhyay, Saibal ^a,b   Mahmoodi, Hamid ^a,b   Roy, Kaushik ^a,b,c,d,e  

^a IEEE

^b Purdue University   (United States)

^c PURDUE UNIVERSITY   (United States)

^d Zenasis Technologies Inc   (United States)

^e MOTOROLA INC   (United States)

Author keywords

Leakage; Performance; Random dopant fluctuation (RDF); Robustness; Synchronous random access memory (SRAM); Yield

Indexed keywords

LEAKAGE; RANDOM DOPANT FLUCTUATION (RDF); ROBUSTNESS; YIELD;

COMPUTER SIMULATION; COMPUTER SYSTEM RECOVERY; MICROPROCESSOR CHIPS; PERFORMANCE; ROBUSTNESS (CONTROL SYSTEMS); STATIC RANDOM ACCESS STORAGE; STATISTICAL METHODS;

CMOS INTEGRATED CIRCUITS;

EID: 29144526605     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.852295     Document Type: Conference Paper

References (25)

1. S. R. Nassif, "Modeling and analysis of manufacturing variations," in Proc. Custom Integrated Circuit Conf., San Diego, CA, 2001, pp. 223-228.
2. C. Visweswariah, "Death, taxes and failing chips," in Proc. Design Automation Conf., Anaheim. CA, 2003, pp. 343-347.
3. S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, "Parameter variation and impact on circuits and microarchitecture," in Proc. Design Automation Conf., Anaheim, CA, 2003, pp. 338-342.
4. A. Bhavnagarwala, X. Tang, and J. D. Meindl. "The impact of intrinsic device fluctuations on CMOS SRAM cell stability," IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 658-665, Apr. 2001.
5. X. Tang, V. De, and J. D. Meindl, "Intrinsic MOSFET parameter fluctuations due to random dopant placement," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 5. no. 4. pp. 369-376, Dec. 1997.
6. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. New York: Cambridge Univ. Press, 1998.
7. D. Burnett, K. Erington, C. Subramanian. and K. Baker, "Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits." in Symp. VLSI Technology. Honolulu, HI, Jun. 1994, pp. 15-16.
8. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Modeling and estimation of failure probability due to parameter variation in nano-scale SRAMs for yield enhancement," in Dig. Tech. Papers VLSI Circuit Symp., Honolulu, HI, Jun. 2004, pp. 64-67.
9. _, "Statistical design and optimization of SRAM cell for yield enhancement," in Proc. Int. Conf. Computer Aided Design, San Jose, CA, Nov. 2004, pp. 10-13.
10. S. Mukhopadhyay, A. Raychowdhury, and K. Roy, "Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling," in Design Automation Conf., Anaheim, CA, Jun. 2003, pp. 169-174.
11. D. A. Antoniadis, I. J. Djomehri, K. M Jackson, and S. Miller, "Well-Tempered," Bulk-Si NMOSFET Device Home Page. Cambridge, MA:Microsystems Technologies Laboratories, Massachusetts Institute of Technology [Online], Available: http://www-mtl.mit.edu/Well/
12. MEDICI: 2-D Device Simulation Program. Mountain View, CA: Synopsys Inc.
13. A. Papoulis, Probability, Random Variables and Stochastic Process. New York: MacGraw-Hill, 2002.
14. A. Chandrakasan, W. J. Bowhill, and F. Fox, Design of High-Performance Microprocessor Circuits. Piscataway, NJ: IEEE Press, 2001.
15. H. Qin, Y. Cao, D. Markovic, A. Vladimirescu, and J. Rabaey, "SRAM leakage suppression by minimizing standby supply voltage," in Int. Symp. Quality Electronic Design, San Jose, CA, Mar. 2004, pp. 55-60.
16. R. W. Mann et al., "Ultralow-power SRAM technology," IBM J. Res. Develop., vol. 47, no. 5/6, pp. 553-566, Sep. 2003.
17. B. W. Wah and Y.-X. Chen, "Constrained genetic algorithms and their applications in nonlinear constrained optimization," in IEEE Int. Conf. Tools Artificial Intelligence, Vancouver, BC, Canada. Nov. 2000, pp. 286-293.
18. E. K. P. Chong and S. H. Zak, An Introduction to Optimization. New York: Wiley, 2001.
19. t low-leakage gated-ground cache for deep submicron," IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 319-328, Feb. 2003.
20. A. Chen, "Redundancy in LSI memory array," IEEE J. Solid-State Circuits, vol. 4, no. 5. pp. 291-293, Oct. 1969.
21. S. E. Schuster, "Multiple word/bit line redundancy for semiconductor memories," IEEE J. Solid-State Circuits, vol. 13, no. 5, pp. 698-703, Oct. 1978.
22. J. R. Day, "A fault-driven, comprehensive redundancy algorithm," IEEE Des. Test Comput., vol. 2, no. 2, pp. 35-44, Jun. 1985.
23. W.-K. Huang, Y.-N. Shen, and F. Lombardi, "New approaches for the repair of memories with redundancy by row/column deletion for yield enhancement," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 9, no. 3, pp. 323-328, Mar. 1990.
24. C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, "Built-in redundancy analysis for memory yield improvement," IEEE Trans. Reliab., vol. 52, no. 4, pp. 386-399, Dec. 2003.
25. C. H. Stapper, A. N. McLaren, and M. Dreckmann, "Yield model for productivity optimization of VLSI memory chips with redundancy and partially good product," IBM J. Res. Develop., vol. 24, no. 3, pp. 398-409, 1980.