A statistical approach to area-constrained yield enhancement for pipelined circuits under parameter variations

Proceedings of the Asian Test Symposium

Volumn 2005, Issue , 2005, Pages 170-175

  Datta, Animesh ^a   Bhunia, Swarup ^a   Mukhopadhyay, Saibal ^a   Roy, Kaushik ^a  

^a Purdue University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONSTRAINT THEORY; OPTIMIZATION; PARAMETER ESTIMATION; STATISTICAL METHODS;

AREA-CONSTRAINED YIELD ENHANCEMENT; OPTIMIZATION RESULTS; PIPELINED CIRCUITS; TARGET DELAY CONSTRAINT;

NETWORKS (CIRCUITS);

EID: 33645803195     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2005.16     Document Type: Conference Paper

References (10)

1. K. A. Bowman et al., "Impact of Die-to-Die and Within-Die Parameter Fluctuations on the Maximum Clock Frequency Distribution for Gigascale Integration", JSSC'02, pp. 183-190.
2. S. Choi et al., "Novel Sizing Algorithm for Yield Improvement under Process Variation in Nanometer Technology", DAC 2004, pp. 454-459.
3. J. L. Hennessy et al., "Computer Architecture: A Quantitative Approach", Morgan Kaufmann, May 2002.
4. C. Chen et al., "Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation", IEEE TCAD'99, Vol. 18, No. 7, 1999, pp. 1014-1025.
5. S. Borkar et al., "Parameter Variations and Impact on Circuits and Microarchitecture", DAC 2003, pp. 338-342.
6. H. Mahmoodi et al., "Estimation of Delay Variations Due to Random-dopant Fluctuations in Nano-Scaled CMOS circuits", CICC 2004, pp. 17-20.
7. S. G. Duvall, "Statistical circuit modeling and optimization", IWSM, June 2000, pp. 56-63.
8. C. E. Clark, "The Greatest of a Finite Set of Random Variables," Operation Research, vol. 9, 1961, pp. 85-91.
9. H. Chang et al., "Statistical timing analysis considering spatial correlations using a single pert-like traversal", ICCAD 2003, pp. 621-625.
10. A. Datta et al., "Statistical Modeling of Pipeline Delay and Design of Pipeline under Process variation to Enhance Yield in sub-100nm Technology", DATE 2005, pp. 926-931.