NBTI Induced performance degradation in logic and memory circuits: How effectively can we approach a reliability solution?

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2008, Pages 726-731

  Kang, Kunhyuk ^a   Gangwal, Saakshi ^a   Park, Sang Phill ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; DEGRADATION; DIGITAL INTEGRATED CIRCUITS; INDUSTRIAL ENGINEERING; INTEGRATED CIRCUIT MANUFACTURE; NEGATIVE TEMPERATURE COEFFICIENT; NETWORKS (CIRCUITS); RANDOM PROCESSES; SULFATE MINERALS; THERMODYNAMIC STABILITY;

CIRCUIT APPLICATIONS; CIRCUIT DESIGNS; DESIGN AUTOMATION CONFERENCE; DESIGN TECHNIQUES; INDUCED DEGRADATION; MEMORY ARRAYS; MEMORY CELLS; MEMORY CIRCUITS; NBTI DEGRADATION; NEGATIVE BIAS- TEMPERATURE-INSTABILITY; PERFORMANCE DEGRADATION; PROCESS VARIATIONS; READ STABILITY; SIMULATION RESULTS; SINGLE TRANSISTORS; SOUTH PACIFIC;

LOGIC CIRCUITS;

EID: 49549087051     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2008.4484047     Document Type: Conference Paper

References (39)

1. D. K. Schroder and J. A. Babcock, "Negative Bias Temperature Instability: Road to cross in deep submicron silicon semiconductor manufacturing," J. App. Phys., 2003.
2. K. Jeppson and C. Svensson, "Negative bias of MOS devices at high electric fields and degradation of MNOS devices," J. App. Phys., 1977.
3. M. A. Alam, "A critical examination of the mechanics of dynamic NBTI for PMOSFETs," IEDM, 2003.
4. A. T. Krishnan et al., "Negative bias temperature instability mechanism: The role of molecular hydrogen," APL, 2006.
5. S. Chakravarthi et al., "A comprehensive framework for predictive modeling of negative bias temperature instability," IRPS, 2004.
6. G. Chen et al., "Dynamic NBTI of PMOS transistors and its impact on device lifetime," IRPS, 2003.
7. N. Kimizuka et al., "Impact of bias temperature instability for direct tunneling ultrathin gate oxide on MOSFET scaling," VLSI Tech. Symp.,1999.
8. Robert F. Pierret, "Semiconductor Device Fundamentals," Addison Wesley 1996.
9. International Technology Roadmap for Semiconductors, http://www.itrs.net/
10. S. Borkar et al., "Parameter variations and impact on circuits and microarchitecture," DAC, 2003.
11. D. Varghese et al., "On the dispersive versus arrhenius temperature activation of nbti time evolution in plasma nitrided gate oxides: measurements, theory, and implications," IEDM, 2005.
12. A. E. Islam et al., "Critical analysis of short-term negative bias temperature instability measurements: Explaining the effect of time-zero delay for on-the-fly measurements," APL, 2007.
13. T. Yang et al., "Fast DNBTI components in p-MOSFET with SiON dielectric," EDL, 2005.
14. C. Shen et al., "Characterization and physical origin of fast Vth transient in NBTI of pMOSFETs with SiON dielectric," IEDM, 2006.
15. H. Reisinger et al., "Analysis of NBTI degradation and recovery behavior based on ultra fast vt measurements," IRPS, 2006.
16. R. Fernandez et al., "An NBTI studied in the 1Hz 2GHz range on dedicated on-chip CMOS circuits," IEDM, 2006.
17. W. Abadeer and W. Ellis "Behavior of NBTI under AC dynamic circuit conditions," IRPS, 2003.
18. B. C. Paul et al., "Impact of NBTI on the temporal performance degradation of digital circuits," EDL, 2005.
19. S. V. Kumar et al., "An analytical model for negative bias temperature instability," ICCAD, 2006.
20. R. Vattikonda et al., "Modeling and minimization of PMOS NBTI effect for robust nanometer design," DAC, 2006.
21. Predictive Technology Model, http://www.eas.asu.edu/∼ptm/
22. Y. H. Lee et al., "Effect of pMOST Bias Temperature Instability on Circuit Reliability Performance," IEDM, 2003.
23. DDQ Measurement," DAC, 2007.
24. B. C. Paul et al., "Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits," DATE, 2006.
25. K. Kang et al., "Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI," ICCD, 2006.
26. S. Kumar et al., "NBTI-Aware Synthesis of Digital Circuits," DAC, 2007.
27. R. Burch et al., "A Monte Carlo Approach for Power Estimation," TVLSI, 1993.
28. T. Kim et al., "Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits," VLSI Circ. Symp., 2007.
29. K. Kang et al., "Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop," DAC, 2007.
30. M. Agarwal et al., "Circuit Failure Prediction and Its Application to Transistor Aging," VTS, 2007.
31. S. Kumar et al., "Impact of NBTI on SRAM Read Stability and Design for Reliability", ISQED, 2006.
32. DDQ," ITC, 2007
33. E. Seevinck et al., "Static-noise margin analysis of MOS SRAM cells," JSSC, 1987.
34. A. Bhavnagarwala et al., "The impact of intrinsic device fluctuations on CMOS SRAM cell stabilitiy," JSSC, 2001.
35. S. Mukhopadhyay et al., "Statistical design and optimization of SRAM cell for yield enhancement," ICCAD, 2004
36. Ik Joon Chang et al., "Fast and Accurate Estimation of Nano-Scaled SRAM Read Failure Probability using Critical Point Sampling," CICC, 2005.
37. H. Qin et al., "SRAM Leakage Suppression by Minimizing Standby Supply Voltage," ISQED, 2004.
38. S. Mukhopadhyay et al., "Self-Repairing SRAM for Reducing Parametric Failures in Nanoscaled Memory," VLSI Circ. Symp., 2006
39. S. Tan et al., "Mechanism of Nitrogen-Enhanced Negative Bias Temperature Instability in PMOSFET," Microelectron. Reliab. J., 2004