A process-tolerant cache architecture for improved yield in nanoscale technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 1, 2005, Pages 27-37

  Agarwal, Amit ^a   Paul, Bipul C ^a   Mahmoodi, Hamid ^a   Datta, Animesh ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

Process tolerant cache; Resizing; SRAM failures; Yield

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SYSTEM RECOVERY; DOPING (ADDITIVES); ERROR CORRECTION; FAULT TOLERANT COMPUTER SYSTEMS; MICROPROCESSOR CHIPS; NANOTECHNOLOGY; PROBABILITY DENSITY FUNCTION; STATIC RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE;

PROCESS-TOLERANT CACHE; RESIZING; SRAM FAILURES; YIELD;

BUFFER STORAGE;

EID: 13144266757     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.840407     Document Type: Article

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