-
2
-
-
0142196052
-
Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation
-
Oct
-
T. Chen and S. Naffziger, "Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 10, pp. 888-899, Oct. 2003.
-
(2003)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, vol.11
, Issue.10
, pp. 888-899
-
-
Chen, T.1
Naffziger, S.2
-
3
-
-
39749141962
-
Optimum threshold-voltage tuning for low-power high-performance microprocessor
-
M. Miyazaki, G. Ono, and T. Kawahara, "Optimum threshold-voltage tuning for low-power high-performance microprocessor," in Proc. IEEE Int. Symp. Circuits Syst., 2005, pp. 17-20.
-
(2005)
Proc. IEEE Int. Symp. Circuits Syst
, pp. 17-20
-
-
Miyazaki, M.1
Ono, G.2
Kawahara, T.3
-
4
-
-
22544455956
-
Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems
-
Jul
-
L. Yan, J. Luo, and N. K. Jha, "Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 24, no. 7, pp. 1030-1041, Jul. 2005.
-
(2005)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst
, vol.24
, Issue.7
, pp. 1030-1041
-
-
Yan, L.1
Luo, J.2
Jha, N.K.3
-
5
-
-
0346148512
-
Combined dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems
-
L. Yan, J. Luo, and N. K. Jha, "Combined dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems," in Proc. IEEE Int. Conf. Comput.-Aided Des., 2003, pp. 30-37.
-
(2003)
Proc. IEEE Int. Conf. Comput.-Aided Des
, pp. 30-37
-
-
Yan, L.1
Luo, J.2
Jha, N.K.3
-
6
-
-
0036917242
-
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads
-
S. M. Martin, K. Flautner, T. Mudge, and D. Blaauw, "Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads," in Proc. IEEE Int. Conf. Comput.-Aided Des., 2002, pp. 721-725.
-
(2002)
Proc. IEEE Int. Conf. Comput.-Aided Des
, pp. 721-725
-
-
Martin, S.M.1
Flautner, K.2
Mudge, T.3
Blaauw, D.4
-
7
-
-
21744455802
-
Energy-aware supply and body biasing voltage scheduling algorithm
-
S. Yajuan, W. Zuodong, and W. Shaojun, "Energy-aware supply and body biasing voltage scheduling algorithm," in Proc. Int. Conf. Solid State Integr. Circuits Technol., 2004, pp. 1956-1959.
-
(2004)
Proc. Int. Conf. Solid State Integr. Circuits Technol
, pp. 1956-1959
-
-
Yajuan, S.1
Zuodong, W.2
Shaojun, W.3
-
8
-
-
3042565410
-
Over-head-conscious voltage selection for dynamic and leakage energy reduction of time-constrained systems
-
A. Andrei, M. Schmitz, P. Eles, Z. Peng, and B. M. Al-Hashimi, "Over-head-conscious voltage selection for dynamic and leakage energy reduction of time-constrained systems," in Proc. Des., Autom. Test Eur., 2004, pp. 518-523.
-
(2004)
Proc. Des., Autom. Test Eur
, pp. 518-523
-
-
Andrei, A.1
Schmitz, M.2
Eles, P.3
Peng, Z.4
Al-Hashimi, B.M.5
-
9
-
-
0029484356
-
Channel doping engineering of MOSFET with adaptable threshold voltage using body effect for low voltage and low power applications
-
C. H. Wann, H. Chenming, K. Noda, D. Sinitsky, F. Assaderaghi, and J. Bokor, "Channel doping engineering of MOSFET with adaptable threshold voltage using body effect for low voltage and low power applications," in Proc. Int. Symp. VLSI Technol., 1995, pp. 159-163.
-
(1995)
Proc. Int. Symp. VLSI Technol
, pp. 159-163
-
-
Wann, C.H.1
Chenming, H.2
Noda, K.3
Sinitsky, D.4
Assaderaghi, F.5
Bokor, J.6
-
10
-
-
0030086605
-
A 0.9 V 150 MHz 10 mW 2-D discrete cosine transform core processor with variable-threshold-voltage scheme
-
T. Kuroda, T. Fujita, S. Mita, T. Nagamatu, S. Yoshioka, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, and T. Sakurai, "A 0.9 V 150 MHz 10 mW 2-D discrete cosine transform core processor with variable-threshold-voltage scheme," in Proc. IEEE Int. Solid-State Circuits Conf., 1996, pp. 166-167.
-
(1996)
Proc. IEEE Int. Solid-State Circuits Conf
, pp. 166-167
-
-
Kuroda, T.1
Fujita, T.2
Mita, S.3
Nagamatu, T.4
Yoshioka, S.5
Sano, F.6
Norishima, M.7
Murota, M.8
Kako, M.9
Kinugawa, M.10
Kakumu, M.11
Sakurai, T.12
-
11
-
-
0036858210
-
Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage
-
Nov
-
J. W. Tschanz, J. Kao, S. G. Narendra, R. Nair, D. Antoniadis, A. Chandrakasan, and V. De, "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1396-1402, Nov. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, Issue.11
, pp. 1396-1402
-
-
Tschanz, J.W.1
Kao, J.2
Narendra, S.G.3
Nair, R.4
Antoniadis, D.5
Chandrakasan, A.6
De, V.7
-
12
-
-
39749185147
-
Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power
-
J. Tschanz, S. Narendra, A. Keshavarazi, and V. De, "Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power," in Proc. IEEE Int. Symp. Circuits Syst., 2005, pp. 9-12.
-
(2005)
Proc. IEEE Int. Symp. Circuits Syst
, pp. 9-12
-
-
Tschanz, J.1
Narendra, S.2
Keshavarazi, A.3
De, V.4
-
13
-
-
0242720765
-
Dynamic sleep transistor and body bias for active leakage power control of microprocessors
-
Nov
-
J. W. Tschanz, S. G. Narendra, Y. Ye, B. A. Bloechel, S. Borkar, and V. De, "Dynamic sleep transistor and body bias for active leakage power control of microprocessors," IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1838-1845, Nov. 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.11
, pp. 1838-1845
-
-
Tschanz, J.W.1
Narendra, S.G.2
Ye, Y.3
Bloechel, B.A.4
Borkar, S.5
De, V.6
-
14
-
-
0038528639
-
Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors
-
May
-
J. W. Tschanz, S. G. Narendra, R. Nair, and V. De, "Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors," IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 26-829, May 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.5
, pp. 26-829
-
-
Tschanz, J.W.1
Narendra, S.G.2
Nair, R.3
De, V.4
-
15
-
-
0037852928
-
Forward body bias for microprocessors in 130-nm technology generation and beyond
-
May
-
S. Narendra, A. Keshavarzi, B. A. Bloechel, S. Borkar, and V. De, "Forward body bias for microprocessors in 130-nm technology generation and beyond," IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 696-701, May 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.5
, pp. 696-701
-
-
Narendra, S.1
Keshavarzi, A.2
Bloechel, B.A.3
Borkar, S.4
De, V.5
-
16
-
-
17644420047
-
Temperature referenced supply voltage and forward-body-bias control (TSFC) architecture for minimum power consumption
-
G. Ono, M. Miyazaki, H. Tanaka, N. Ohkubo, and T. Kawahara, "Temperature referenced supply voltage and forward-body-bias control (TSFC) architecture for minimum power consumption," in Proc. Euro. Solid State Circuits Conf., 2004, pp. 391-394.
-
(2004)
Proc. Euro. Solid State Circuits Conf
, pp. 391-394
-
-
Ono, G.1
Miyazaki, M.2
Tanaka, H.3
Ohkubo, N.4
Kawahara, T.5
-
17
-
-
39749148123
-
-
Device Group, Arizona State University, Tempe, Predictive technology model, 2006 [Online]. Available: http:www-eas.asu.edu/ptm
-
Device Group, Arizona State University, Tempe, "Predictive technology model," 2006 [Online]. Available: http:www-eas.asu.edu/ptm
-
-
-
-
18
-
-
16244401645
-
Larger-than-vdd forward body bias in sub -0.5 V nanoscale CMOS
-
H. Ananthan, C. H. Kim, and K. Roy, "Larger-than-vdd forward body bias in sub -0.5 V nanoscale CMOS," in Proc. IEEE Int. Symp. Low Power Electron. Des., 2004, pp. 8-13.
-
(2004)
Proc. IEEE Int. Symp. Low Power Electron. Des
, pp. 8-13
-
-
Ananthan, H.1
Kim, C.H.2
Roy, K.3
-
19
-
-
0242527271
-
Design and modeling challenges for 90 nm and 50 nm
-
V. Gerousis, "Design and modeling challenges for 90 nm and 50 nm," in Proc. IEEE Custom Integr. Circuit Conf., 2003, pp. 353-360.
-
(2003)
Proc. IEEE Custom Integr. Circuit Conf
, pp. 353-360
-
-
Gerousis, V.1
-
20
-
-
34548812547
-
Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging
-
J. W. Tschanz, N. S. Kim, S. Dighe, J. Howard, G. Ruhl, S. Vangal, S. Narendra. Y. Hoskote. H. Wilson, C. Lam, M. Shuman, C. Tokunaga, D. Somasekhar, S. Tang, D. Finan, T. Karnik, N. Borkar, N. Kurd, and V. De, "Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging," in Proc. IEEE Int. Solid-State Circuits Conf., 2007, pp. 292-294.
-
(2007)
Proc. IEEE Int. Solid-State Circuits Conf
, pp. 292-294
-
-
Tschanz, J.W.1
Kim, N.S.2
Dighe, S.3
Howard, J.4
Ruhl, G.5
Vangal, S.6
Narendra, S.7
Hoskote, Y.8
Wilson, H.9
Lam, C.10
Shuman, M.11
Tokunaga, C.12
Somasekhar, D.13
Tang, S.14
Finan, D.15
Karnik, T.16
Borkar, N.17
Kurd, N.18
De, V.19
-
22
-
-
0242527271
-
Design and modeling challenges for 90 nm and 50 nm
-
V. Gerousis, "Design and modeling challenges for 90 nm and 50 nm," in Proc. IEEE Custom Integr. Circuits Conf., 2003, pp. 353-360.
-
(2003)
Proc. IEEE Custom Integr. Circuits Conf
, pp. 353-360
-
-
Gerousis, V.1
-
23
-
-
33746080003
-
Handling inverted temperature dependence in static Timing analysis
-
Apr
-
A. Dasdan and I. Horn, "Handling inverted temperature dependence in static Timing analysis," ACM Trans. Des. Autom. Election. Syst., vol. 11, pp. 306-324, Apr. 2006.
-
(2006)
ACM Trans. Des. Autom. Election. Syst
, vol.11
, pp. 306-324
-
-
Dasdan, A.1
Horn, I.2
-
24
-
-
0035473305
-
Design impact of positive temperature dependence on D rain current in sub-IV CMOS VLSIs
-
K. Kanda, K. Nose, H. Kawaguchi, and T. Sakurai, "Design impact of positive temperature dependence on D rain current in sub-IV CMOS VLSIs," in Proc. IEEE Custom Integr. Circuits Conf., 1999, pp. 1559-1564.
-
(1999)
Proc. IEEE Custom Integr. Circuits Conf
, pp. 1559-1564
-
-
Kanda, K.1
Nose, K.2
Kawaguchi, H.3
Sakurai, T.4
-
25
-
-
39749124705
-
-
E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Sal-danha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni- Vincentelli, SIS: A system for sequential circuit synthesis, Univ. California, Berkeley, Tech. Rep. UCB/ERL M92/41, 1992 [Online]. Available: http://www-cad.eecs.berkeley.edu/research/sis
-
E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Sal-danha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni- Vincentelli, "SIS: A system for sequential circuit synthesis," Univ. California, Berkeley, Tech. Rep. UCB/ERL M92/41, 1992 [Online]. Available: http://www-cad.eecs.berkeley.edu/research/sis
-
-
-
|