CRISTA: A new paradigm for low-power, variation-tolerant, and adaptive circuit synthesis using critical path isolation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 11, 2007, Pages 1947-1956

  Ghosh, Swaroop ^a   Bhunia, Swarup ^b   Roy, Kaushik ^a  

^a Purdue University   (United States)

^b CASE WESTERN RESERVE UNIVERSITY   (United States)

Author keywords

Low power; Process variation tolerant design; Supply voltage scaling; Temperature aware design

Indexed keywords

ADAPTIVE CIRCUITS; ADAPTIVENESS; BENCHMARK CIRCUITS; BERKELEY PREDICTIVE TECHNOLOGY MODELS; CIRCUIT DESIGNS; CONVENTIONAL DESIGNS; CRITICAL PATHS; CYCLE OPERATIONS; DESIGN CONSIDERATIONS; DESIGN REQUIREMENTS; DIE AREAS; LOW POWER; LOW-POWER DESIGNS; LOW-POWER OPERATIONS; NEGATIVE IMPACTS; PARAMETRIC YIELDS; PIPELINE DESIGNS; PROCESS VARIATION-TOLERANT DESIGN; SIMULATION RESULTS; SINGLE CYCLES; SUPPLY VOLTAGE SCALING; SUPPLY VOLTAGES; TEMPERATURE-AWARE DESIGN; VOLTAGE-SCALING;

BENCHMARKING; INTEGRATED CIRCUIT MANUFACTURE; PIPELINES; TIMING CIRCUITS;

DESIGN;

EID: 54249104938     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2007.896305     Document Type: Article

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