The impact of intrinsic device fluctuations on CMOS SRAM cell stability

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 4, 2001, Pages 658-665

  Bhavnagarwala, Azeez J ^a,b   Tang, Xinghai ^a,b   Meindl, James D ^a,b  

^a IEEE   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

MOSFET fluctuations; SRAM scaling; SRAM stability projections; Static noise margin

Indexed keywords

CELL STABILITY; INTRINSIC THRESHOLD VOLTAGE FLUCTUATIONS; STATIC NOISE MARGIN; STOCHASTIC MODELS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; DELTA SIGMA MODULATION; MICROPROCESSOR CHIPS; MOSFET DEVICES; SEMICONDUCTOR DEVICE MODELS; SIGNAL NOISE MEASUREMENT; STATIC RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE; VOLTAGE MEASUREMENT;

INTEGRATED CIRCUIT TESTING;

EID: 0035308547     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.913744     Document Type: Article

References (13)

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5. Static-noise margin analysis of MOS SRAM cells
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9. The national technology roadmap for semiconductors
10. Worst-case noise margin criteria for logic circuits and their mathematical equivalence
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12. Dynamic threshold CMOS SRAM cells for fast portable applications