First-order incremental block-based statistical timing analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 10, 2006, Pages 2170-2179

  Visweswariah, Chandu ^a,b   Ravindran, Kaushik ^a,b,c   Kalafala, Kerim ^d   Walker, Steven G ^b   Narayan, Sambasivan ^d   Beece, Daniel K ^b   Piaget, Jeff ^d   Venkateswaran, Natesan ^d   Hemmett, Jeffrey G ^d  

^a IEEE   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d IBM MICROELECTRONICS   (United States)

Author keywords

Criticality probability; Incremental timing; Statistical static timing; Variability

Indexed keywords

CRITICALITY PROBABILITY; INCREMENTAL TIMING; STATISTICAL STATIC TIMING; VARIABILITY;

DELAY CIRCUITS; GRAPH THEORY; MATHEMATICAL MODELS; OPTIMIZATION; PROBABILITY; ROBUSTNESS (CONTROL SYSTEMS); TIME DOMAIN ANALYSIS; TIMING DEVICES;

DIGITAL INTEGRATED CIRCUITS;

EID: 33748329641     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.862751     Document Type: Article

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