Modeling and analysis of manufacturing variations

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2001, Pages 223-228

  Nassif, S R ^a  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT MANUFACTURE; INTERCONNECTION NETWORKS;

CIRCUIT VARIATIONS; DIE TO DIE SHIFTS; STATIC TIMING ANALYSIS; WORST CASE MODELING;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034833288     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

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5. Buffer insertion with accurate models for gate and interconnect delay
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8. Realistical statistical worst-case simulations of vlsi circuits
9. A critical path delay check system
10. Timing verification and the timing analysis program
11. Developments in logic network path delay analysis
12. LEADOUT: A static timing analyzer for MOS circuits
13. A gate-delay model for high-speed CMOS circuits
14. Circuit limited yield (cly) model development feasibility report