Lifetime reliability: Toward an architectural solution

IEEE Micro

Volumn 25, Issue 3, 2005, Pages 70-80

  Srinivasan, Jayanth ^a,b   Adve, Sarita V ^a   Bose, Pradip ^b   Rivers, Jude A ^b  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC BREAKDOWN; ELECTROMIGRATION; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; MONTE CARLO METHODS; RELIABILITY; THERMODYNAMIC STABILITY; TRANSISTORS;

DYNAMIC RELIABILITY MANAGEMENT (DRM); LIFETIME RELIABILITY; MEAN TIME TO FAILURE (MTTF); MICROARCHITECTURAL INTERVENTION; POWER MANAGEMENT; RELIABILITY-AWARE MICROPROCESSOR (RAMP); SCALING;

MICROPROCESSOR CHIPS;

EID: 22944456833     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2005.54     Document Type: Article

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