Self-calibrating online wearout detection

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2007, Pages 109-120

  Blome, Jason ^a   Feng, Shuguang ^a   Gupta, Shantanu ^a   Mahlke, Scott ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC BATTERIES; FAILURE ANALYSIS; FORECASTING; GATES (TRANSISTOR); MECHANISMS; MODEL STRUCTURES; QUALITY ASSURANCE; STANDARDS; TECHNOLOGY;

DEVICE FAILURES; EMBEDDED MICROPROCESSORS; FAILURE MECHANISMS; FEATURE SIZES; FUTURE TECHNOLOGY; GATE OXIDE BREAKDOWN (GOX-BD); GATE OXIDES; HARDWARE STRUCTURES; INTERNATIONAL SYMPOSIUM; LEVEL STRUCTURES; MICRO ARCHITECTURES; MICROPROCESSOR CORES; OUTPUT DELAYS; PHYSICAL ANALYSES; PROPAGATION DELAYS; SELF-CALIBRATING; STANDARD-CELL LIBRARIES; STATISTICAL ANALYSIS (IGC: E4/K7); TECHNOLOGY SCALING; VERILOG; VOLTAGE SCALING;

RELIABILITY;

EID: 47249158717     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2007.35     Document Type: Conference Paper

References (41)

1. Gartner data systems conference, Dec. 2005.
2. International technology roadmap for semiconductors, 2005.
3. Openrisc 1200, 2006. http://www.opencores.org/projects.cgi/web/or1k/ openrisc 1200.
4. Ridgetop group, 2006. http://www.ridgetop-group.com/.
5. M. Agarwal, B. Paul, and S. Mitra. Circuit failure prediction and its application to transistor aging. In Proc. of the 2007 IEEE VLSI Test Symposium, page To appear, Apr. 2007.
6. E. R. Alliance. Online survey results: 2001 cost of downtime, 2001.
7. J. S. S. T. Association. Failure mechanisms and models for semiconductor devices. Technical Report JEP122C, JEDEC Solid State Technology Association, Mar. 2006.
8. T. Austin. Diva: a reliable substrate for deep submicron microarchitecture design. In Proc. of the 32nd Annual International Symposium on Microarchitecture, pages 196-207, 1999.
9. T. Austin, D. Blaauw, T. Mudge, and K. Flautner. Making typical silicon matter with razor. IEEE Computer, 37(3):57-65, Mar. 2004.
10. M. Batty. Monitoring an exponential smoothing forecasting system. Operational Research Quaterly, 20(3):319-325, 1969.
11. B. G. U. Berkeley. Bsim4 mosfet model, 2007.
12. D. Bernick, B. Bruckert, P. D. Vigna, D. Garcia, R. Jardine, J. Klecka, and J. Smullen. Nonstop Advanced Architecture. In International Conference on Dependable Systems and Networks, pages 12-21, June 2005.
13. J. A. Blome, S. Feng, S. Gupta, and S. Mahlke. Online timing analysis for wearout detection. In Proc. of the 2nd Workshop on Architectural Reliability (WAR), pages 51-60, 2006.
14. S. Borkar. Designing reliable systems from unreliable components: The challenges of transistor variability and degradation. IEEE Micro, 25(6):10-16, 2005.
15. F. A. Bower, D. J. Sorin, and S. Ozev. A mechanism for online diagnosis of hard faults in microprocessors. In Proc. of the 38th Annual International Symposium on Microarchitecture, pages 197-208, 2005.
16. J. Carter, S. Ozev, and D. Sorin. Circuit-level modeling for concurrent testing of operational defects due to gate oxide breadkown. In Proc. of the 2005 Design, Automation and Test in Europe, pages 300-305, June 2005.
17. D. Ernst, N. S. Kim, S. Das, S. Pant, T. Pham, R. Rao, C. Ziesler, D. Blaauw, T. Austin, and T. Mudge. Razor: A low-power pipeline based on circuit-level timing speculation. In Proc. of the 36th Annual International Symposium on Microarchitecture, pages 7-18, 2003.
18. M. Gomaa and T. Vijaykumar. Opportunistic transient-fault detection. In Proc. of the 32nd Annual International Symposium on Computer Architecture, pages 172-183, June 2005.
19. T. Kehl. Hardware self-tuning and circuit performance monitoring. In Proc. of the 1993 International Conference on Computer Design, pages 188-192, Oct. 1993.
20. B. P. Linder and J. H. Stathis. Statistics of progressive breakdown in ultra-thin oxides. Microelectronic Engineering, 72(1-4):24-28, 2004.
21. F. Monsieur, E. Vincent, D. Roy, S. Bruyere, J. C. Vildeuil, G. Pananakakis, and G. Ghibaudo. A thorough investigation of progressive breakdown in ultra-thin oxides. physical understanding and application for industrial reliability assessment. In Proc. of the 2002 International Reliability Physics Symposium, pages 45-54, Apr. 2002.
22. J. Ray, J. Hoe, and B. Falsafi. Dual use of superscalar datapath for transient-fault detection and recovery. In Proc. of the 34th Annual International Symposium on Microarchitecture, pages 214-224, Dec. 2001.
23. V. Reddy, S. Parthasarathy, and E. Rotenberg. Understanding prediction-based partial redundant threading for low-overhead, high-coverage fault tolerance. In 14th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 83-94, Oct. 2006.
24. S. K. Reinhardt and S. S. Mukherjee. Transient fault detection via simulataneous multithreading. In Proc. of the 27th Annual International Symposium on Computer Architecture, pages 25-36, June 2000.
25. G. Reis, J. Chang, N. Vachharajani, R. Rangan, , and D. I. August. SWIFT: Software implemented fault tolerance. In Proc. of the 2005 International Symposium on Code Generation and Optimization, pages 243-254, 2005.
26. R. Rodriguez, J. H. Stathis, and B. P. Linder. Modeling and experimental verification of the effect of gate oxide breakdown on cmos inverters. In International Reliability Physics Symposium, pages 11-16, Apr. 2003.
27. E. Rotenberg. AR-SMT: A microarchitectural approach to fault tolerance in microprocessors. In International Symposium on Fault Tolerant Computing, pages 84-91, 1999.
28. P. Shivakumar, S. Keckler, C. Moore, and D. Burger. Exploiting microarchitectural redundancy for defect tolerance. In Proc. of the 2003 International Conference on Computer Design, page 481, Oct. 2003.
29. K. Skadron, M. R. Stan, K. Sankaranarayanan, W. Huang, S. Velusamy, and D. Tarjan. Temperature-aware microarchitecture: Modeling and implementation. ACM Transactions on Architecture and Code Optimization, 1(1):94-125, 2004.
30. J. Smolens, J. Kim, J. Hoe, and B. Falsafi. Efficient resource sharing in concurrent error detecting superscalar microarchitectures. In Proc. of the 37th Annual International Symposium on Microarchitecture, pages 256-268, Dec. 2004.
31. A. Sodani and G. Sohi. Dynamic instruction reuse. In Proc. of the 25th Annual International Symposium on Computer Architecture, pages 194-205, June 1998.
32. L. Spainhower and T. Gregg. IBM S/390 Parallel Enterprise Server G5 Fault Tolerance: A Historical Perspective. IBM Journal of Research and Development, 43(6):863-873, 1999.
33. J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers. The case for lifetime reliability-aware microprocessors. In Proc. of the 31st Annual International Symposium on Computer Architecture, pages 276-287, June 2004.
34. J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers. Exploiting structural duplication for lifetime reliability enhancement. In Proc. of the 32nd Annual International Symposium on Computer Architecture, pages 520-531, June 2005.
35. StockCharts.com. TRIX, Oct. 2006. http://stockcharts.com/ education/IndicatorAnalysis/indic trix.htm.
36. J. Sune and E. Wu. From oxide breakdown to device failure: an overview of post-breakdown phenomena in ultrathin gate oxides. In International Conference on Integrated Circuit Design and Technology, pages 1-6, May 2006.
37. T. Vijaykumar, I. Pomeranz, and K. Cheng. Transient-fault recovery via simultaneous multithreading. In Proc. of the 29th Annual International Symposium on Computer Architecture, pages 87-98, May 2002.
38. N. Wang and S. Patel. Restore: Symptom based soft error detection in microprocessors. In International Conference on Dependable Systems and Networks, pages 30-39, June 2005.
39. E. Wu et al. Interplay of voltage and temperature acceleration of oxide breakdown for ultra-thin gate oxides. Solid-State Electronics, 46:1787-1798, 2002.
40. T. J. Yamaguchi, M. Soma, D. Halter, J. Nissen, R. Raina, M. Ishida, and T. Watanabe. Jitter measurements of a powerpc microprocessor using an analytic signal method. In Proc. of the 2000 International Test Conference, pages 955-964, 2000.
41. X. Yang, E. Weglarz, and K. Saluja. On nbti degradation process in digital logic circuits. In Proc. of the 2007 International Conference on VLSI Design, pages 723-730, Jan. 2007.