Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell

ESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference

Volumn , Issue , 2004, Pages 211-214

  Joshi, Rajiv V ^a   Mukhopadhyay, Saibal ^b   Plass, Donald W ^c   Chan, Yuen H ^c   Chuang, Ching Te ^a   Devgan, A ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b PURDUE UNIVERSITY   (United States)

^c IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PERFORMANCE DEGRADATION; SRAM CELL; STATIC NOISE MARGIN (SNM); VARIABILITY ANALYSIS;

ELECTRIC POTENTIAL; PERFORMANCE; RANDOM ACCESS STORAGE; ROBUSTNESS (CONTROL SYSTEMS); SILICON ON INSULATOR TECHNOLOGY; TRANSISTORS;

CMOS INTEGRATED CIRCUITS;

EID: 17644374580     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. V. De et. al., "Technology and design challenges for low power & high performance", Proc. ISLPED, 1999, pp. 163-168.
2. A.J. Bhavnagarwala, et. al., "The impact of intrinsic device fluctuations on CMOS SRAM cell stability,' IEEE Journal of Solid-State Circuits, vol. 36, pp. 658-665, April 2001.
3. R.V. Joshi, et. al., "High Performance SRAMs in 1.5V 0.18 μm partially depleted SOI technology", Dig. Tech. Papers, Symp. VLSI Circuits, 2002. pp. 74- 77.
4. A.Chandrakasan, et. al., Design of High-Performance Microprocessor Circuits, Ed. Piscataway, NJ: IEEE, ch. 14, 2001.
5. R.V. Joshi, et. al., "Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM", Dig. Tech. Papers, Symp. VLSI Technology, 2001, pp. 75-76.