Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2005, Issue , 2005, Pages 736-741

  Agarwal, Amit ^a   Kunhyuk, Kang ^a   Roy, Kaushik ^a  

^a Purdue University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; LOGIC GATES; MATHEMATICAL MODELS; MONTE CARLO METHODS; TOPOLOGY; TRANSISTORS;

CIRCUIT LEAKAGE DISTRIBUTION; STATISTICAL INFORMATION;

CHIP SCALE PACKAGES;

EID: 33751441014     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560162     Document Type: Conference Paper

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