Variation-aware gate sizing and clustering for post-silicon optimized circuits

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2008, Pages 105-110

  Zhuo, Cheng ^a   Blaauw, David ^a   Sylvester, Dennis ^a  

^a The Department of Civil and Environmental Engineering   (United States)

Author keywords

Body bias; Clustering; Optimization; Sizing; Variation

Indexed keywords

ADAPTIVE BODY BIASING; BODY BIAS; CLUSTERING; DELAY CONSTRAINTS; GATE SIZINGS; INDUSTRIAL TEST CASE; LINEAR DEPENDENCES; LOOK-UP MODELS; OPTIMIZATION METHODOLOGIES; POST SILICONS; PROCESS VARIATIONS; RE-CLUSTERING; RUN-TIME; SIZING; STANDARD CELLS; VARIATION; VLSI DESIGNS;

ELECTRIC BATTERIES; GATES (TRANSISTOR); LOW POWER ELECTRONICS; OPTIMIZATION; POWER ELECTRONICS; PROBABILITY DISTRIBUTIONS; TUNING;

CLUSTERING ALGORITHMS;

EID: 57549087415     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1393921.1393949     Document Type: Conference Paper

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