Design and reliability challenges in nanometer technologies

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 75-

  Borkar, Shekhar ^a   Karnik, Tanay ^a   De, Vivek ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Leakage tolerance; Low power; Reliability; Soft errors; Variation tolerance

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; FREQUENCIES; LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; RELIABILITY; SILICON ON INSULATOR TECHNOLOGY; STATIC RANDOM ACCESS STORAGE;

LEAKAGE TOLERANCE; LOW-POWER; SOFT ERRORS; VARIATION TOLERANCE;

NANOTECHNOLOGY;

EID: 4444272791     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996588     Document Type: Conference Paper

References (2)

1. T. Karnik, S. Borkar, V. De, "Sub 90-nm Technologies-challenges and opportunities for CAD", IEEE ICCAD, pp. 203-206, Nov. 2002.
2. S. Borkar, et al., "Parameter Variations and Impact on Circuits and Microarchitecture," ACM/IEEE DAC, pp. 338-342, June 2003.