-
1
-
-
0003144772
-
Device and technology impact on low power electronics
-
J. Rabaey, Ed. Norwell, MA: Kluwer
-
C. Hu, "Device and technology impact on low power electronics, " in Low Power Design Methodologies, J. Rabaey, Ed. Norwell, MA: Kluwer, 1996, pp. 21-35.
-
(1996)
Low Power Design Methodologies
, pp. 21-35
-
-
Hu, C.1
-
2
-
-
1642327694
-
-
[Online]
-
[Online]. Available: http://developer.intel.com/design/mobile/datashts
-
-
-
-
3
-
-
0036049564
-
High-performance and low-power challenges for sub-70 nm microprocessor circuits
-
R. K. Krishnamurthy, A. Alvandpour, V. De, and S. Borkar, "High-performance and low-power challenges for sub-70 nm microprocessor circuits," in Proc. CICC, 2002, pp. 125-128.
-
(2002)
Proc. CICC
, pp. 125-128
-
-
Krishnamurthy, R.K.1
Alvandpour, A.2
De, V.3
Borkar, S.4
-
4
-
-
0032680122
-
Models and algorithms for bounds on leakage in CMOS circuits
-
June
-
M. C. Johnson, D. Somasekhar, and K. Roy, "Models and algorithms for bounds on leakage in CMOS circuits," IEEE Trans. Computer-Aided Design, vol. 18, pp. 714-725, June 1999.
-
(1999)
IEEE Trans. Computer-aided Design
, vol.18
, pp. 714-725
-
-
Johnson, M.C.1
Somasekhar, D.2
Roy, K.3
-
5
-
-
0029359285
-
1-V power supply high-speed digital circuit technology with multithreshold voltage CMOS
-
Aug.
-
S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "1-V power supply high-speed digital circuit technology with multithreshold voltage CMOS," IEEE J. Solid-State Circuits, vol. 30, pp. 847-854, Aug. 1995.
-
(1995)
IEEE J. Solid-state Circuits
, vol.30
, pp. 847-854
-
-
Mutoh, S.1
Douseki, T.2
Matsuya, Y.3
Aoki, T.4
Shigematsu, S.5
Yamada, J.6
-
6
-
-
0032688692
-
Standby power minimization through simultaneous threshold voltage and circuit sizing
-
S. Sirichotiyakul, T. Edwards, C. Oh, J. Zuo, A. Dharchoudhury, R. Panda, and D. Blaauw, "Standby power minimization through simultaneous threshold voltage and circuit sizing," in Proc. DAC, 1999, pp. 436-441.
-
(1999)
Proc. DAC
, pp. 436-441
-
-
Sirichotiyakul, S.1
Edwards, T.2
Oh, C.3
Zuo, J.4
Dharchoudhury, A.5
Panda, R.6
Blaauw, D.7
-
7
-
-
0031635212
-
A new technique for standby leakage reduction in high-performance circuits
-
Y. Ye, S. Borkar, and V. De, "A new technique for standby leakage reduction in high-performance circuits," in Proc. Symp. VLSI Circuits, 1998, pp. 40-41.
-
(1998)
Proc. Symp. VLSI Circuits
, pp. 40-41
-
-
Ye, Y.1
Borkar, S.2
De, V.3
-
8
-
-
0030712582
-
A gate-level leakage power reduction method for ultra-low-power CMOS circuits
-
J. Halter and F. Najm, "A gate-level leakage power reduction method for ultra-low-power CMOS circuits," in Proc. CICC, 1997, pp. 475-478.
-
(1997)
Proc. CICC
, pp. 475-478
-
-
Halter, J.1
Najm, F.2
-
9
-
-
0030697754
-
Transistor sizing issues and tool for multi-threshold CMOS technology
-
J. Kao, A. Chandrakasan, and D. Antoniadis, "Transistor sizing issues and tool for multi-threshold CMOS technology," in Proc. DAC, 1997, pp. 409-414.
-
(1997)
Proc. DAC
, pp. 409-414
-
-
Kao, J.1
Chandrakasan, A.2
Antoniadis, D.3
-
10
-
-
0032667127
-
th (MVT) cmos circuit design methodology for low power applications
-
th (MVT) cmos circuit design methodology for low power applications," in Proc. DAC, 1999, pp. 430-435.
-
(1999)
Proc. DAC
, pp. 430-435
-
-
Wei, L.1
Chen, Z.2
Roy, K.3
Ye, Y.4
De, V.5
-
12
-
-
0020142882
-
CAD model for threshold and subthreshold conduction in MOSFET's
-
June
-
P. Antognetti, "CAD model for threshold and subthreshold conduction in MOSFET's," IEEE J. Solid State Circuits, vol. SC-17, pp. 454-458, June 1982.
-
(1982)
IEEE J. Solid State Circuits
, vol.SC-17
, pp. 454-458
-
-
Antognetti, P.1
-
13
-
-
0030681185
-
Device-circuit optimization for minimal energy and power consumption in CMOS random logic networks
-
P. Pant, V. De, and A. Chatterjee, "Device-circuit optimization for minimal energy and power consumption in CMOS random logic networks," in Proc. DAC, 1997, pp. 403-408.
-
(1997)
Proc. DAC
, pp. 403-408
-
-
Pant, P.1
De, V.2
Chatterjee, A.3
-
15
-
-
33646900503
-
Device scaling limits of Si MOSFET's and their application dependencies
-
Mar.
-
D. J. Frank, R. Dennard, E. Nowak, P. Solomon, Y. Taur, and H. P. Wong, "Device scaling limits of Si MOSFET's and their application dependencies," Proc. IEEE, vol. 89, pp. 259-288, Mar. 2001.
-
(2001)
Proc. IEEE
, vol.89
, pp. 259-288
-
-
Frank, D.J.1
Dennard, R.2
Nowak, E.3
Solomon, P.4
Taur, Y.5
Wong, H.P.6
-
16
-
-
0036949325
-
Full chip subthreshold leakage power prediction model for sub -0.18 μm CMOS
-
S. Narendra, V. De, S. Borkar, and A. Chandrakasan, "Full chip subthreshold leakage power prediction model for sub -0.18 μm CMOS," in Proc. ISLPED, 2002, pp. 139-23.
-
(2002)
Proc. ISLPED
, pp. 139-223
-
-
Narendra, S.1
De, V.2
Borkar, S.3
Chandrakasan, A.4
-
17
-
-
0034452603
-
t transistors and 6 layers of Cu interconnect
-
t transistors and 6 layers of Cu interconnect," in Proc. IEDM, 2000, pp. 567-570.
-
(2000)
Proc. IEDM
, pp. 567-570
-
-
Tyagi, S.1
Alavi, M.2
Bigwood, R.3
Bramblett, T.4
Tyagi, S.5
Bradenburg, J.6
Chen, W.7
Crew, B.8
Hussein, M.9
Jacob, P.10
Kenyon, C.11
Lo, C.12
McIntyre, B.13
Ma, Z.14
Moon, P.15
Nguyen, P.16
Rumaner, L.17
Schweinfurth, R.18
Sivakumar, S.19
Stettler, M.20
Thompson, S.21
Tufts, B.22
Xu, J.23
Yang, S.24
Bohr, M.25
more..
-
18
-
-
0036907029
-
Subthreshold leakage modeling and reduction techniques
-
Nov.
-
J. Kao, S. Narendra, and A. Chandrakasan, "Subthreshold leakage modeling and reduction techniques," in Proc. ICCAD, Nov. 2002, pp. 141-148.
-
(2002)
Proc. ICCAD
, pp. 141-148
-
-
Kao, J.1
Narendra, S.2
Chandrakasan, A.3
-
19
-
-
0036954781
-
Modeling and analysis of leakage power considering within-die process variations
-
A. Srivastava, R. Bai, D. Blaauw, and D. Sylvester, "Modeling and analysis of leakage power considering within-die process variations," in Proc. ISLPED, 2002, pp. 64-67.
-
(2002)
Proc. ISLPED
, pp. 64-67
-
-
Srivastava, A.1
Bai, R.2
Blaauw, D.3
Sylvester, D.4
-
22
-
-
0027684546
-
An improved generalized guide for MOSFET scaling
-
K. K. Ng, S. A. Eshraghi, and T. D. Stanik, "An improved generalized guide for MOSFET scaling," IEEE Trans. Electron Devices, vol. 40, pp. 1893-1895, 1993.
-
(1993)
IEEE Trans. Electron Devices
, vol.40
, pp. 1893-1895
-
-
Ng, K.K.1
Eshraghi, S.A.2
Stanik, T.D.3
-
23
-
-
0031621934
-
Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks
-
Z. Chen, M. Johnson, L. Wei, and K. Roy, "Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks," in Proc. ISLPED, 1998, pp. 239-244.
-
(1998)
Proc. ISLPED
, pp. 239-244
-
-
Chen, Z.1
Johnson, M.2
Wei, L.3
Roy, K.4
-
24
-
-
0028017169
-
Comparison of methods of computing lognormal sum distributions and outages for digital wireless applications
-
N. C. Beaulieu, A. A. Abu-Dayya, and P. J. McLane, "Comparison of methods of computing lognormal sum distributions and outages for digital wireless applications," in Proc. IEEE Int. Conf. Communications, vol. 3, 1994, pp. 1270-1275.
-
(1994)
Proc. IEEE Int. Conf. Communications
, vol.3
, pp. 1270-1275
-
-
Beaulieu, N.C.1
Abu-Dayya, A.A.2
McLane, P.J.3
-
25
-
-
0020180746
-
On the distribution function and moments of power sums with lognormal components
-
Sept.
-
S. C. Schwartz and Y. S. Yeh, "On the distribution function and moments of power sums with lognormal components," Bell Syst. Tech. J., vol. 61, pp. 1441-1462, Sept. 1982.
-
(1982)
Bell Syst. Tech. J.
, vol.61
, pp. 1441-1462
-
-
Schwartz, S.C.1
Yeh, Y.S.2
-
26
-
-
0003016939
-
A normal limit theorem for power sums of independent random variables
-
Nov.
-
N. Marlow, "A normal limit theorem for power sums of independent random variables," Bell Syst. Tech. J., vol. 46, pp. 2081-2090, Nov. 1967.
-
(1967)
Bell Syst. Tech. J.
, vol.46
, pp. 2081-2090
-
-
Marlow, N.1
-
27
-
-
1642402342
-
-
personal communication
-
K Bernstein, personal communication, 2003.
-
(2003)
-
-
Bernstein, K.1
-
28
-
-
0002609165
-
A neutral netlist of 10 combinational benchmark circuits and a target translator in fortran
-
May
-
F. Brglez and H. Fujiwara, "A neutral netlist of 10 combinational benchmark circuits and a target translator in fortran," in Proc. Int. Symp. Circuits and Systems, May 1985, pp. 695-698.
-
(1985)
Proc. Int. Symp. Circuits and Systems
, pp. 695-698
-
-
Brglez, F.1
Fujiwara, H.2
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