Polymorphic on-chip networks

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2008, Pages 101-112

  Kim, Martha Mercaldi ^a   Davis, John D ^b   Oskin, Mark ^a   Austin, Todd ^c  

^a UNIVERSITY OF WASHINGTON   (United States)

^b MICROSOFT RESEARCH   (United States)

^c UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONFIGURABILITY; GAIN PERFORMANCE; INTERCONNECT DESIGN; INTERNATIONAL SYMPOSIUM; MEMORY BLOCKS; NETWORK ARCHITECTURE DESIGN; NETWORK AREA; NETWORK DESIGNS; NETWORK-ON-CHIP DESIGN; ON-CHIP INTERCONNECTS; ON-CHIP NETWORKS; OPTIMAL PERFORMANCES; PARETO-OPTIMAL; PERFORMANCE ANALYSES; RUN-TIME; TRAFFIC PATTERNS;

COMPUTER ARCHITECTURE; COMPUTER SCIENCE; COMPUTER SYSTEMS; COMPUTERS; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUITS; NETWORK ARCHITECTURE; OPTICAL INTERCONNECTS;

ARCHITECTURAL DESIGN;

EID: 52649174496     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2008.25     Document Type: Conference Paper

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