Duet: An accurate leakage estimation and optimization tool for dual-V t circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 2, 2002, Pages 79-90

  Sirichotiyakul, Supamas ^a,b   Edwards, Tim ^c   Oh, Chanhee ^a,c   Panda, Rajendran ^a,c   Blaauw, David ^a,d  

^a IEEE   (United States)

^b SUN MICROSYSTEMS   (United States)

^c MOTOROLA INC   (United States)

^d University of Michigan   (United States)

Author keywords

Critical path; Dual V t; High performance; Leakage; Low power design; Low power dissipation; Low voltage; Performance tradeoffs

Indexed keywords

DOMINANT LEAKAGE STATES; GRAPH REDUCTION TECHNIQUES; POWER DISSIPATION; SOFTWARE PACKAGE SPICE; STATE PROBABILITIES;

ALGORITHMS; CALCULATIONS; COMPUTER SIMULATION; LEAKAGE CURRENTS; MOSFET DEVICES; PROBABILITY; THRESHOLD VOLTAGE;

DIGITAL INTEGRATED CIRCUITS;

EID: 0036543067     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.994980     Document Type: Article

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