A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 1, 2008, Pages 180-191

  Nii, Koji ^a   Yabuuchi, Makoto ^a   Tsukamoto, Yasumasa ^a   Ohbayashi, Shigeki ^a   Imaoka, Susumu ^b   Makino, Hiroshi ^a   Yamagami, Yoshinobu ^c   Ishikura, Satoshi ^c   Terano, Toshio ^c   Oashi, Toshiyuki ^a   Hashimoto, Keiji ^a   Sebe, Akio ^c   Okazaki, Gen ^c   Satomi, Katsuji ^c   Akamatsu, Hironori ^c   Shinohara, Hirofumi ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b Renesas Design Corporation   (Japan)

^c PANASONIC CORPORATION   (Japan)

Author keywords

45 nm bulk CMOS; Assist circuit; memory cell; read margin; SRAM; static noise margin (SNM); Vth variation; write margin

Indexed keywords

EID: 85008042429     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.2007.907998     Document Type: Article

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