Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2006, Pages 19-26

  Mani, Murari ^a   Singh, Ashish K ^a   Orshansky, Michael ^a  

^a The University of Texas at Austin   (United States)

Author keywords

Algorithms; Design; Reliability

Indexed keywords

(100) SILICON; (R ,S ,S) POLICY; ADAPTIVE BODY BIAS (ABB); AFFINE FUNCTIONS; BENCHMARK CIRCUITS; BODY BIASING; CHIP-LEVEL; CIRCUIT PARAMETERS; CO-OPTIMIZATION; COMPUTATIONAL TRACTABILITY; COMPUTER-AIDED DESIGN; CONTROL AND MEASUREMENT; FORMAL OPTIMIZATION; GA TE LENGTHS; INTERNATIONAL CONFERENCES; JOINT DESIGNS; LEAKAGE POWER; MEASUREMENT AND CONTROL; METRICS (CO); OPTIMAL POLICIES; OPTIMIZATION STRATEGIES; PARAMETRIC YIELD LOSS; ROBUST OPTIMIZATION; RUN TIME; SPATIAL STRUCTURING; STATISTICAL FORMULATION; TIME OPTIMIZATION; UNCERTAIN VARIABLES; VARIABLE PARAMETERS;

CAPACITANCE; DESIGN; ENERGY CONSERVATION; FUNCTION EVALUATION; LINEAR PROGRAMMING; LINEARIZATION; NETWORKS (CIRCUITS); PARAMETER ESTIMATION; SHAPE OPTIMIZATION; STRUCTURAL OPTIMIZATION;

OPTIMIZATION;

EID: 46149117523     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320100     Document Type: Conference Paper

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