Statistical analysis of SRAM cell stability

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 57-62

  Agarwal, Kanak ^a   Nassif, Sani ^a  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

Modeling; Noise margin; Reliability; SRAM; Stability

Indexed keywords

ACOUSTIC NOISE; COMPUTER SIMULATION; DC MACHINERY; MONTE CARLO METHODS; RELIABILITY; STATISTICAL METHODS;

CELL FAILURE PROBABILITIES; NOISE MARGIN; PROCESS VARIATION; THEORETICAL FRAMEWORK;

STATIC RANDOM ACCESS STORAGE;

EID: 34547210880     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1146928     Document Type: Conference Paper

References (18)

1. M. Orshansky, L. Milor, P. Chen, K. Keutzer, C. Hu, "Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits", ICCAD 2000, pp. 62-67.
2. V. Mehrotra et al. "A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance", DAC, 2000, pp. 172-175.
3. B. Stine, D. Boning, J. Chung, "Analysis and decomposition of spatial variation in integrated circuit processes and devices", IEEE Trans on Semiconductor Manufacturing, 1997, pp. 24-41.
4. R.W. Keyes, "The impact of randomness in the distribution of impurity atoms on FET threshold", Journal of Applied Physics, 1975, pp. 251-259.
5. X. Tang, V. De, J. Meindl, "Intrinsic MOSFET parameter placement due to random placement", IEEE Trans on VLSI, 1997, pp. 369-376.
6. D. Burnett, K. Erington, C. Subramanian, K. Baker, "Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits", Symp on VLSI Tech, 1994, pp. 15-16.
7. B. Cheng, S. Roy, A. Asenov, "The impact of random doping effects on CMOS SRAM cell", European Solid State Circuits Conf, 2004, pp. 219-222.
8. M. Pelgrom, A. Duinmaijer, A. Welbers, "Matching properties of MOS transistors", JSSC, 1989, pp. 1433-1440.
9. T. Mizuno, J. Okamura, A. Toriumi, "Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFETs", IEEE Trans on Electron Devices, 1194, pp. 2216-2221.
10. K. Lakshmikumar, R. Hadaway, M.A. Copeland, "Characterization and modeling of mismatch in MOS transistors for precision analog design", JSSC, 1986, pp. 1057-1066.
11. R. Heald, P. Wang, 'Variability in sub-100nm SRAM designs", ICCAD, 2004, pp. 347-352.
12. E. Seevinck, F. List, J. Lohstroh, "Static-noise margin analysis of MOS transistors", JSSC, 1987, pp. 748-754.
13. A. Bhavanagarwala, X. Tang, J. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability, JSSC, 2001, pp. 658-665.
14. S. Mukhopadhyay, H. Mahmoodi, K. Roy, "Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscale CMOS", IEEE Trans on Computer-Aided Design, 2005, pp. 1859-1880.
15. R. Joshi et al. "Variability analysis of sub-100 nm PD/SOI CMOS SRAM cell", Europe Solid State Circuits Conf, 2004, pp. 211-214.
16. J. Lohstroh, E. Seevinck, J. Groot, "Worst-case static noise margin criteria for logic circuits and their mathematical equivalence", JSSC, 1983, pp. 803-806.
17. T. Sakurai, A.R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter," JSSC, 1990, pp. 584-594.
18. E. Leobandung et al., "High-performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell", Symp on VLSI Technology, 2005, pp. 126-127.