A process-variation-tolerant floating-point unit with voltage interpolation and variable latency

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 404-623

  Liang, Xiaoyao ^a   Brooks, David ^a   Wei, Gu Yeon ^a  

^a HARVARD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL ARITHMETIC; INTERPOLATION;

CRITICAL PATH DELAYS; FLOATING POINT UNITS; INTERPOLATION SCHEMES; MEDIAN FREQUENCY; POST-FABRICATION; PROCESS VARIATION; TUNING RANGES; VARIABLE LATENCIES;

TUNING;

EID: 49549096924     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523228     Document Type: Conference Paper

References (5)

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3. H. Li, et al., "Combined circuit and architecture level variable supply-voltage scaling for low power," Trans. VLSI, May 2005.
4. C. Tran, et al., "95% Leakage-Reduced FPGA using Zigzag power-gating, dual-Vth/Vdd and micro-Vdd-hopping," ASSCC Dig. Tech. Papers, Nov. 2005.
5. K. Agarwal, K. Nowka, "Dynamic Power management by combination of dual static supply voltages," Int. Symp. Quality Elec. Design, Mar. 2007.