Temporal performance degradation under NBTI: Estimation and design for improved reliability of nanoscale circuits

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Paul, Bipul C ^a   Kang, Kunhyuk ^b   Kufluoglu, Haldun ^b   Alarn, Muhammad Ashraful ^b   Roy, Kaushik ^b  

^a Toshiba America Research Inc   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BIAS CURRENTS; RELIABILITY ANALYSIS; SYSTEMS ANALYSIS;

BENCHMARK CIRCUITS; DELAY DEGRADATION; NANOSCALE CIRCUITS; NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI);

LOGIC CIRCUITS;

EID: 34047187067     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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