SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 4, 2005, Pages 895-900

  Zhang, Kevin ^a   Bhattacharya, Uddalak ^a   Chen, Zhanping ^a   Hamzaoglu, Fatih ^a   Murray, Daniel ^a   Vallepalli, Narendra ^a   Wang, Yih ^a   Zheng, B ^a   Bohr, Mark ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Leakage reduction; Sleep transistor; SRAM; Weak write test mode

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; LEAKAGE CURRENTS; SPURIOUS SIGNAL NOISE; TRANSISTORS; VLSI CIRCUITS; VOLTAGE CONTROL;

LEAKAGE REDUCTION; SLEEP TRANSISTORS; VOLTAGE SCALING; WEAK-WRITE TEST MODE;

STATIC RANDOM ACCESS STORAGE;

EID: 18744365842     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.842846     Document Type: Conference Paper

References (9)

1. 2 full-CMOS SRAM cell with aspect ratio of 0.63 in a high-performance 0.25 μm-generation CMOS technology," in Symp. VLSI Technology Dig. Tech. Papers, Jun. 1998, pp. 68-69.
2. K. Zhang, K. Hose, V. De, and B. Senyk, "The scaling of data sensing schemes for high speed cache design in sub-0.18 μm technologies," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2000, pp. 226-227.
3. K. Zhang et al., "A fully synchronized, pipelined, and re-configurable 50 Mb SRAM on 90 nm CMOS technology for logic applications," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2003, pp. 253-254.
4. J. Maiz, S. Hareland, K. Zheng, and P. Armstrong, "Characterization of multi-bit soft-error events in advanced SRAMs," in IEDM Tech. Dig., Dec. 2003, pp. 519-522.
5. A. Bhavnagarwala, S. V. Kosonocky, M. Immediate, D. Knebel, and A.-M. Haen, "A pico-joule class, 1 GHz, 32 kB 64 b DSP SRAM with self reversed bias," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2003, pp. 251-252.
6. M. Yamaoka et al., "A 300 MHz 25 A/Mb leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, vol. 542, Feb. 2004, pp. 494-495.
7. t low-leakage gated-ground cache for deep submicron," IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 319-328, Feb. 2003.
8. DD control (RRDV) scheme," in Proc. IEEE Int. ASIC/SOC Conf., Sep. 2002, pp. 381-385.
9. DD SRAM's," in Proc. IEEE Int. Symp. Low Power Electronics and Design (ISLPED), Aug. 2003, pp. 66-71.