Rapid estimation of the probability of SRAM failure due to MOS threshold variations

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2007, Pages 229-232

  Srivastava, Shweta ^a   Roychowdhury, Jaijeet ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; MATHEMATICAL MODELS; MOS DEVICES; SPICE; THRESHOLD VOLTAGE;

BOUNDARY CURVE; EULER-NEWTON CURVE TRACING; MEMORY ARRAYS; STATIC NOISE MARGIN;

STATIC RANDOM ACCESS STORAGE;

EID: 39549089375     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405720     Document Type: Conference Paper

References (12)

1. S. R. Nassif. Modeling and Analysis of Manufacturing Variations. In Proc. IEEE Custom Integrated Circuits Conference, pages 223-228, 2001.
2. Q. Chen, H. Mahmoodi, S. Bhunia, and K. Roy. Efficient Testing of SRAM With Optimized March Sequences and a Novel DFT Technique for Emerging Failures Due to Process Variations. IEEE Transactions on Very Large Scale Integration Systems, 13:1286-1295, November 2005.
3. X. Li, B. Huang, X. Zhang, and J. B. Bernstein. SRAM Circuit-Failure Modeling and Reliability Simulation With SPICE. IEEE Transactions on Device and Materials Reliability, 6:235-246, June 2006.
4. S. Mukhopadhyay, H. Mahmoodi, S. Bhunia, and K. Roy. Modeling of Failure Probability and Statistical Design of SRAM Array for Yield Enhancement in Nanoscaled CMOS. IEEE Transactions on Computer-Aided Design Of Integrated Circuits and Systems, 24:1859-1880, December 2005.
5. Y. Tsukamoto, K. Nii, S. Imaoka, Y. Oda, and S. Ohbayashi. Worst-Case Analysis to Obtain Stable Read/Write DC Margin of High Density 6T-SRAM-Array with Local Vth Variability. In Proc. IEEE/ACM International Conference on Computer-Aided Design, pages 398-405, November 2005.
6. J. Roychowdhury and R. Melville. Delivering Global DC Convergence for Large Mixed-Signal Circuits via Homotopy/Continuation Methods. IEEE Transactions on Computer-Aided Design, January 2006.
7. S. Srivastava and J. Roychowdhury. Rapid and Accurate Latch Characterization via Direct Newton Solution of Setup/Hold Times. In Proc. IEEE Design, Automation, and Test in Europe Conference, April 2007.
8. S. Srivastava and J. Roychowdhury. Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-Transition Equations. In Proc. IEEE Design Automation Conference, June 2007.
9. L. O. Chua and P. M. Lin. Computer-Aided Analysis of Electronic Circuits: Algorithms and Computation Techniques. Prentice-Hall, Englewood Cliffs, NJ, 1975.
10. E. L. Allgower and K. Georg. Numerical Continuation Methods. Springer-Verlag, New York, 1990.
11. C. W. Gear. Numerical Initial Value Problems in Ordinary Differential Equations. Prentice-Hall series in automatic computation. Prentice-Hall, Englewood Cliffs, N.J., 1971.
12. S. Nassif. SRAM Memory Cell Modeling, February 2007. Digital Technology Center, University of Minnesota.