A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 3, 2007, Pages 680-688

  Calhoun, Benton Highsmith ^a,b   Chandrakasan, Anantha P ^a,c  

^a IEEE   (United States)

^b University of Virginia   (United States)

^c USA   (United States)

Author keywords

Low voltage memory; Sub threshold SRAM; Voltage scaling

Indexed keywords

LOW-VOLTAGE MEMORY; SUB-THRESHOLD SRAM; VOLTAGE SCALING;

COSTS; DATA REDUCTION; ELECTRIC POTENTIAL; ENERGY CONSERVATION; VOLTAGE MEASUREMENT;

STATIC RANDOM ACCESS STORAGE;

EID: 33847724635     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.891726     Document Type: Article

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