Process-tolerant low-power adaptive pipeline under scaled-vdd

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2007, Pages 733-736

  Ghosh, Swaroop ^a   Batra, Pooja ^a   Kim, Keejong ^a   Roy, Kaushik ^a  

^a Purdue University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC LINES; ELECTRIC POTENTIAL; ELECTRIC POWER TRANSMISSION; INTEGRATED CIRCUIT LAYOUT;

ADAPTIVE PIPELINES; CLOCK PERIOD; VOLTAGE SCALING;

MICROPROCESSOR CHIPS;

EID: 39549083080     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405835     Document Type: Conference Paper

References (6)

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4. S. H. Choi et al., Novel sizing algorithm for yield improvement under process variation in nanometer, DAC, 2004.
5. K. Kang et al., Statistical timing analysis using levelized covariance propagation, DATE, 2005.
6. J. Rabaey, Digital integrated circuits, Prentice hall, 1996.