Dynamic-threshold CMOS SRAM cells for fast, portable applications

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 2000, Pages 359-363

  Bhavnagarwala, Azeez J ^a   Kapoor, Ashok ^a,b   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; SCHEMATIC DIAGRAMS; TRANSISTORS; TRIGGER CIRCUITS;

SOFTWARE PACKAGE HSPICE; STATIC RANDOM ACCESS MEMORY;

RANDOM ACCESS STORAGE;

EID: 0033715762     PISSN: 10630988     EISSN: None     Source Type: Journal    
DOI: 10.1109/ASIC.2000.880764     Document Type: Article

References (13)

1. R. W. Keyes The Effect of Randomness in the Distribution of Impurity Atoms on FET Threshold App. Phys. 8 251 259 1975
2. T. Mizuno J. Okamura A. Toriumi Experimental Study of Threshold Voltage Fluctuations using an 8K MOSFET Array Symp. VLSI Tech. 41 42 Symp. VLSI Tech. 1993-Jun.
3. J. D. Meindl Impact of Stochastic Dopant and Interconnect Distributions on Gigascale Integration Proceedings of the 1997 IEEE ISSCC 232 233 Proceedings of the 1997 IEEE ISSCC 1997-February
4. K. Itoh Low Power Memory Dsgn. Tutorial, 1997 ISLPED Tutorial, 1997 ISLPED
5. B. Bateman High Performance SRAM Design Tutorial, ISSCC Tutorial, ISSCC 1998-Feb.
6. E. Seevinck F. List J. Lohstroh Static-Noise Margin Analysis of MOS SRAM Cells IEEE JSSC SC-22 5 748 754 Oct. 1987
7. M. Inohara Highly Scalable and Fully Logic Compatible SRAM Cell Technology with Metal Damascene Process and W Local Interconnect IEEE Symp. VLSI Tech. 64 65 IEEE Symp. VLSI Tech. 1998-Jun.
8. D. Burger System-Level Implications of Processor-Memory Integration 24 Int'l Symp. on Comp. Arch. 24 Int'l Symp. on Comp. Arch. '97-June
9. K. Itoh Trends in Low Power RAM Circuit Technologies Proc. IEEE 83 4 524 543 Apr '95
10. M. Ishida A Novel 6T-SRAM Cell Technology Designed with Rectangular Patterns Scalable beyond 0.18mm Generation and Desirable for Ultra High Speed Operation IEDM Dig. of Tech. papers IEDM Dig. of Tech. papers 1998-Dec.
11. K Itoh A Deep Sub-V, Single Power-Supply SRAM Cell with Multi-VT, Boosted Storage Node and Dynamic Load IEEE Symp. VLSI Ckts. 132 133 IEEE Symp. VLSI Ckts. 1996-Jun
12. H. Mizuno Driving Source Line (DSL) Cell Architecture for Sub 1-V High Speed Low Power Applications 1995 Symp. VLSI Ckts. 25 26 1995 Symp. VLSI Ckts.
13. H Yamauchi A 0.8/1000MHz/sub-5mW Operated Mega-bit SRAM Cell Architecture with Charge Recycle Offset-Source Driving (OSD) Scheme 1996 Symp. VLSI Ckts. 126 127 1996 Symp. VLSI Ckts.