A 32 kb 10T sub-threshold sram array with bit-interleaving and differential read scheme in 90 nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 2, 2009, Pages 650-658

  Chang, Ik Joon ^a   Kim, Jae Joon ^b   Park, Sang Phill ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Low voltage SRAM design; Robust subthreshold operation of SRAM; Voltage scaling in SRAM

Indexed keywords

CELLS; CMOS INTEGRATED CIRCUITS; CYTOLOGY; ERROR CORRECTION; LEAKAGE CURRENTS; LOGIC DESIGN; MICROPROCESSOR CHIPS; THRESHOLD ELEMENTS;

90NM CMOS; BIT LINES; BIT-INTERLEAVING; CELL ARRAYS; CELL STABILITIES; ERROR-CORRECTING CODES; LEAKAGE POWER; LOW ENERGIES; LOW VOLTAGE SRAM DESIGN; MEASUREMENT RESULTS; MEMORY CELLS; PARAMETER VARIATIONS; ROBUST SUBTHRESHOLD OPERATION OF SRAM; SCALED TECHNOLOGIES; SINGLE-ENDED; SOFT ERRORS; SOFT-ERROR TOLERANCES; SRAM STABILITIES; STABLE OPERATIONS; SUB THRESHOLDS; SUBTHRESHOLD REGIONS; ULTRA-LOW VOLTAGES; VOLTAGE SCALING IN SRAM; WRITE OPERATIONS;

STATIC RANDOM ACCESS STORAGE;

EID: 59349118349     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2011972     Document Type: Article

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