Razor: A low-power pipeline based on circuit-level timing speculation

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn 2003-January, Issue , 2003, Pages 7-18

  Ernst, D ^a   Kim, Nam Sung ^a   Das, S ^a   Pant, S ^a   Rao, R ^a   Pham, Toan ^a   Ziesler, C ^a   Blaauw, D ^a   Austin, T ^a   Flautner, K ^b   Mudge, T ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

^b ARM LTD   (United Kingdom)

Author keywords

Clocks; Delay; Dynamic voltage scaling; Error correction; Frequency; Pipelines; Silicon; Timing; Tuned circuits; Voltage control

Indexed keywords

CLOCKS; COMPUTER ARCHITECTURE; DELAY CIRCUITS; EMBEDDED SYSTEMS; ENERGY CONSERVATION; ERROR CORRECTION; ERRORS; FLIP FLOP CIRCUITS; LOW POWER ELECTRONICS; MICROPROCESSOR CHIPS; PARAMETRIC DEVICES; PIPELINES; POWER MANAGEMENT; SILICON; SYSTEM-ON-CHIP; VOLTAGE CONTROL; VOLTAGE SCALING; VOLTAGE STABILIZING CIRCUITS;

DELAY; EMBEDDED PROCESSORS; ENVIRONMENTAL VARIATIONS; FREQUENCY; SILICON INTEGRATION; TIMING; TIMING SPECULATIONS; TUNED CIRCUITS;

TIMING CIRCUITS;

EID: 84944408150     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2003.1253179     Document Type: Conference Paper

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