Energy-efficient and metastability-immune timing-error detection and instruction-replay-based recovery circuits for dynamic-variation tolerance

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 402-623

  Bowman, Keith A ^a   Tschanz, James W ^a   Kim, Nam Sung ^a   Lee, Janice C ^a   Wilkerson, Chris B ^a   Lu, Shih Lien L ^a   Karnik, Tanay ^a   De, Vivek K ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY EFFICIENCY; ERROR DETECTION;

ACTIVATION PROBABILITIES; CLOCK FREQUENCY; DYNAMIC VARIATIONS; ENERGY EFFICIENT; INSTRUCTION REPLAY; RESILIENT CIRCUITS; SUPPLY VOLTAGES; TIMING ERROR DETECTION;

TIMING CIRCUITS;

EID: 49549122926     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523227     Document Type: Conference Paper

References (6)

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3. 2 SRAM Cell," in IEDM Dig. Tech. Papers, pp. 657-660, Dec. 2004.
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5. R. McGowen, C. Poirier, C. Bostak et al., "Power and Temperature Control on a 90-nm Itanium Family Processor," IEEE J. Solid State Circuits, vol. 41, pp. 229-237, Jan. 2006.
6. J. Tschanz, N.-S. Kim, S. Dighe et al., "Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging," in ISSCC Dig. Tech. Papers, pp. 292-293, Feb. 2007.