Large-scale read/write margin measurement in 45nm CMOS SRAM arrays

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2008, Pages 42-43

  Guo, Zheng ^a   Carlson, Andrew ^a   Pang, Liang Teck ^a   Duong, Kenneth ^a   Liu, Tsu Jae King ^a   Nikolic, Borivoje ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; STANDARDS; VLSI CIRCUITS;

BIT LINES; HIGH-DENSITY; NOISE MARGINS; ON CHIPS; PARAMETER VARIATIONS; READ STABILITY; SRAM ARRAYS; SRAM CELLS; STANDARD DEVIATIONS; STORAGE NODES; TEST CHIPS; VOLTAGE SWEEP; WORD LINES;

STATIC RANDOM ACCESS STORAGE;

EID: 51949089762     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2008.4585944     Document Type: Conference Paper

References (6)

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5. E. Seevinck et al. IEEE JSSC 1987.
6. S.E. Thompson, et al, IEEE EDL, 2004.