Simultaneous Vt selection and assignment for leakage optimization

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2003-January, Issue , 2003, Pages 146-151

  Srivastava, A ^a  

^a UNIVERSITY OF MARYLAND   (United States)

Author keywords

Circuits; Delay effects; Dynamic voltage scaling; Educational institutions; Leakage current; Logic design; Logic programming; Optimization methods; Permission; Piecewise linear techniques

Indexed keywords

DELAY CIRCUITS; LEAKAGE CURRENTS; LINEAR PROGRAMMING; LOGIC DESIGN; LOGIC PROGRAMMING; LOW POWER ELECTRONICS; NETWORKS (CIRCUITS); POWER ELECTRONICS; THRESHOLD VOLTAGE; VOLTAGE SCALING;

DELAY EFFECTS; EDUCATIONAL INSTITUTIONS; LEAKAGE OPTIMIZATION; MATHEMATICAL FORMULATION; MULTIPLE-THRESHOLD VOLTAGE; OPTIMIZATION METHOD; PERMISSION; PIECEWISE LINEAR APPROXIMATIONS;

PIECEWISE LINEAR TECHNIQUES;

EID: 1542269353     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231851     Document Type: Conference Paper

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