Process variation tolerant 3T1D-based cache architectures

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2007, Pages 15-26

  Liang, Xiaoyao ^a   Canal, Ramon ^b   Wei, Gu Yeon ^a   Brooks, David ^a  

^a HARVARD UNIVERSITY   (United States)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ENERGY CONSERVATION; LOGIC DESIGN; STATIC RANDOM ACCESS STORAGE; SYSTEM STABILITY; TECHNOLOGY;

6T SRAM; ADVANCED TECHNOLOGIES; DATA CACHING; DATA RETENTION TIMES; DYNAMIC MEMORY; INTERNATIONAL SYMPOSIUM; LARGE POWER; LEAKAGE POWER CONSUMPTION; MEMORY ARCHITECTURE(MA); MEMORY CELLS; MICRO ARCHITECTURES; ON CHIP MEMORIES; ON CHIPS; PLACEMENT SCHEMES; PROCESS VARIATIONS; RETENTION TIME (RT); STATIC MEMORY; TECHNOLOGY SCALING;

DATA STORAGE EQUIPMENT;

EID: 47349110026     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2007.40     Document Type: Conference Paper

References (32)

1. A. Agarwal, D. Blaauw, and V. Zolotov. Statistical timing analysis for intra-die process variations with spatial correlations. In International Conference on Computer-Aided Design, November 2003.
2. A. Agarwal, B. C. Paul, H. Mahmoodi, A. Datta, and K. Roy. A process-tolerant cache architecture for improved yield in nanoscale technologies. IEEE Transactions on Very Large Scale Integration Systems, 13(1), January 2005.
3. A. J. Bhavnagarwala, X. Tang, and J. D. Meindl. The impact of intrinsic device fluctuations on CMOS SRAM cell stability. IEEE Journal of Solid-State Circuits, 36(4), April 2001.
4. S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De. Parameter variation and impact on circuits and microarchitecture. In 40th Design Automation Conference, June 2003.
5. K. Bowman, S. Duvall, and J. Meindl. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. Journal of Solid-State Circuits, 37(2), February 2002.
6. D. Burger, J. Goodman, and A. Kagi. The declining effectiveness of dynamic caching for general-purpose microprocessors. Technical Report TR-1216, U.W.-Madison, Computer Science, 1995.
7. B. Cline, K. Chopra, and D. Blaauw. Analysis and modeling of CD variation for statistical static timing. In International Conference on Computer-Aided Design, November 2006.
8. R. Desikan, D. Burger, S. Keckler, and T. Austin. Sim-Alpha: a validated, execution-driven Alpha 21264 simulator. In TR-01-23, CS Department, University of Texas, 2001.
9. P. Friedberg, W. Cheung, and C. J. Spanos. Spatial variability of critical dimensions. In Proceedings of VLSI/ULSI Multilevel Interconnection Conference, 2005.
10. J. Friedrich et al. Design of the Power6 microprocessor. In International Solid-State Circuits Conference, Feb 2007.
11. E. Humenay, D. Tarjan, W. Huang, and K. Skadron. Impact of parameter variations on multicore architectures. In Workshop on Architectural Support for Gigascale Integration (ASGI-06, held in conjuction with ISCA-33), 2006.
12. P. Juang, K. Skadron, M. Martonosi, Z. Hu, D. W. Clark, P. W. Diodato, and S. Kaxiras. Implementing branch predictor decay using quasi-static memory cells. IEEE Transactions on Architecture and Code Optimization, June 2004.
13. S. Kaxiras, Z. Hu, and M. Martonosi. Cache decay: Exploiting generational behavior to reduce cache leakage power. In Proceedings of the International Symposium on Computer Architecture, 2001.
14. M. Khellah, Y. Ye, N. S. Kim, D. Somasekhar, G. Pandya, A. Farhang, K. Zhang, C. Webb, and V. De. Wordline and bitline pulsing schemes for improving SRAM cell stability in low-Vcc 65nm CMOS designs. In 2006 Symposium on VLSI Technology and Circuits, June 2006.
15. N. S. Kim, T. Kgil, K. Bowman, V. De, and T. Mudge. Total power-optimal pipelining and parallel processing under process variations in nanometer technology. In International Conference on Computer-Aided Design, November 2005.
16. D. Lee and R. Katz. Using cache mechanisms to exploit nonrefreshing DRAMs for on-chip memories. Journal of Solid-State Circuits, 26(4):657-661, April 1991.
17. X. Liang and D. Brooks. Mitigating the impact of process variations on processor register files and execution units. In 39th IEEE International Symposium on Microarchitecture, December 2006.
18. W. K. Luk, J. Cai, R. H. Dennard, M. J. Immediato, and S. V. Kosonocky. A 3-transistor DRAM cell with gated diode for enhanced speed and retention time. In 2006 Symposium on VLSI Technology and Circuits, June 2006.
19. W. K. Luk and R. H. Dennard. A novel dynamic memory cell with internal voltage gain. Journal of Solid-State Circuits, 40(4), April 2005.
20. D. Marculescu and E. Talpes. Variability and energy awareness: A microarchitecture-level perspective. In DAC-42, June 2005.
21. K. Meng and R. Joseph. Process variation aware cache leakage management. In International Symposium on Low Power Electronics and Design, October 2006.
22. S. Ozdemir, D. Sinha, G. Memik, J. Adams, and H. Zhou. Yield-aware cache architectures. In 39th IEEE International Symposium on Microarchitecture, December 2006.
23. D. Patterson, T. Anderson, N. Cardwell, R. Fromm, K. Keeton, C. Kozyrakis, R. Thomas, and K. Yelick. A case for intelligent RAM. IEEE Micro, 17(2):34-44, 1997.
24. A. Phansalkar, A. Joshi, L. Eeckhout, and L. K. John. Measuring program similarity: Experiments with SPEC CPU benchmark suites. In IEEE International Symposium on Performance Analysis of Systems and Software, March 2005.
25. H. Pilo, J. Barwin, G. Braceras, C. Browning, S. Burns, J. Gabric, S. Lamphier, M. Miller, A. Roberts, and F. Towler. An SRAM design in 65nm and 45nm technology nodes featuring read and write-assist circuits to expand operating voltage. In 2006 Symposium on VLSI Technology and Circuits, June 2006.
26. B. F. Romanescu, S. Ozev, and D. J. Sorin. Quantifying the impact of process variability on microprocessor behavior. In 2nd Workshop on Architectural Reliability, 2006.
27. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically characterizing large scale program behavior. In International Conference on Architectural Support for Programming Languages and Operating Systems, October 2002.
28. D. Somasekhar, S.-L. Lu, B. Bloechel, K. Lai, S. Borkar, and V. De. A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high density on-chip memory applications. In 31st European Solid-State Circuits Conference, September 2005.
29. A. Tiwari, S. R. Sarangi, and J. Torrellas. Recycle: Pipeline adaptation to tolerate process variation. In Proceedings of the International Symposium on Computer Architecture, 2007.
30. R. K. Venkatesan, S. Herr, and E. Rotenberg. Retention-aware placement in DRAM (RAPID): Software methods for quasi-nonvolatile DRAM. In 12th International Symposium on High-Performance Computer Architecture, February 2006.
31. D. A. Wood, M. D. Hill, and R. E. Kessler. A model for estimating trace-sample miss ratios. In ACM SIGMETRICS, June 1991.
32. W. Zhao and Y. Cao. New generation of predictive technology model for sub-45nm design exploration. In IEEE International Symposium on Quality Electronic Design, 2006.