Read stability and write-ability analysis of SRAM cells for nanometer technologies

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 11, 2006, Pages 2577-2588

  Grossar, Evelyn ^b,c   Stucchi, Michele ^b   Maex, Karen ^a,b,c   Dehaene, Wim ^a,c  

^a IEEE

^b IMEC   (Belgium)

^c UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

Intra die Vth variations; N curve; Read stability and write ability of the SRAM cell; Statistically aware design optimization; V dd scaling

Indexed keywords

CMOS INTEGRATED CIRCUITS; OPTIMIZATION; PRODUCT DEVELOPMENT; ROBUSTNESS (CONTROL SYSTEMS); STATIC RANDOM ACCESS STORAGE; STATISTICAL METHODS;

INTRA-DIE VTH VARIATIONS; N-CURVE; READ STABILITY AND WRITE-ABILITY OF THE SRAM CELLS; STATISTICALLY-AWARE DESIGN OPTIMIZATION;

NANOTECHNOLOGY;

EID: 33750815896     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.883344     Document Type: Conference Paper

References (24)

1. B. Cheng et al., "The impact of random doping effects on CMOS SRAM cell," in Proc. ESSCIRC, Sep. 2004, pp. 219-222.
2. E. Seevinck et al., "Static-noise margin analysis of MOS SRAM cells," IEEE J. Solid-State Circuits, vol. SC-22, no. 5, pp. 748-754, Oct. 1987.
3. A. J. Bhavnagarwala et al., "The impact of intrinsic device fluctuations on CMOS SRAM cell stability," IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 658-665, Apr. 2001.
4. L. Chang et al., "Stable SRAM cell design for the 32 nm node and beyond," in Symp. VLSI Technology Dig. Tech. Papers, Jun. 2005, pp. 128-129.
5. C. Wann et al., "SRAM cell design for stability methodology," in Proc. IEEE VLSI-TSA, Apr. 2005, pp. 21-22.
6. S. Mukhopadhyay et al., "Modeling and estimation of failure probability due to parameter variations in nano-scale SRAMs for yield enhancement," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2004, pp. 64-67.
7. E. Grossar, "A yield-aware modeling methodology for nano-scaled SRAM designs," in Proc. ICICDT, May 2005, pp. 33-36.
8. J. Lohstroh et al., "Worst-case static noise margin criteria for logic circuits and their mathematical equivalence," IEEE J. Solid-State Circuits, vol. SC-18, no. 6, pp. 803-807, Dec. 1983.
9. J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective (2nd edition). Englewood Cliffs, NJ: Prentice Hall.
10. R. Heald et al., "Variability in sub-100 nm SRAM designs," in Proc. IEEE/ACM ICCAD, Nov. 2004, pp. 347-352.
11. K. Roy et al., "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits," Proc. IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003.
12. J. T. Kao et al., "A 175-mV multiply-accumulate unit using an adaptive supply voltage and body bias architecture," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1545-1554, Nov. 2002.
13. E. Grossar et al., "Statistically aware SRAM memory array design," in Proc. IEEE ISQED, San Jose, CA, 2006.
14. K. Itoh, "Low-voltage embedded RAMs in the nanometer era," in Proc. ICICDT '05, pp. 235-242.
15. A. Papoulis, Probability, Random Variables and Stochastic Process. New York: McGraw-Hill, 1991.
16. R. W. Mann et al., "Ultralow-power SRAM technology," IBM J. Res & Dev., vol. 47, no. 5/6, pp. 553-566, Sep./Nov. 2003.
17. C. Rose et al., Mathematical Statistics With Mathematica. New York: Springer-Verlag, 2002.
18. J. Purviance et al., "Statistical performance sensitivity-A valuable measure for manufacturing oriented CAD," in IEEE MTT-S Dig., 1992.
19. th, and sizing," in Proc. IEEE DAC, Jun. 2004, pp. 773-778.
20. P. Geens et al., "A small granular controlled leakage reductions system for SRAMs," J. Solid State Electron., no. 49, pp. 1776-1782, Nov. 2005.
21. J. A. Croon et al., "An easy-to-use mismatch model for the MOS transistor," IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1056-1064, Aug. 2002.
22. B. Tavel et al., "Thin oxynitride solution for digital and mixed-signal 65 nm CMOS platform," in IEDM Tech. Dig., Dec. 2003, p. 27.6.(1-4).
23. "HSPICE Simulation and Analysis User Guide, Version W-2005.03," Synopsys, Mountain View, CA, 2005.
24. Y. Tsukamoto et al., "Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability," in Proc. IEEE/ACM ICCAD, Nov. 2005, pp. 398-405.