Circuit failure prediction and its application to transistor aging

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2007, Pages 277-284

  Agarwal, Mridul ^a   Paul, Bipul C ^b   Zhang, Ming ^c   Mitra, Subhasish ^a  

^a STANFORD UNIVERSITY   (United States)

^b TOSHIBA CORPORATION   (Japan)

^c INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT FAILURE PREDICTION; SIMULATION RESULTS; SYSTEMS PERFORMANCE;

AGING OF MATERIALS; CIRCUIT SIMULATION; COSTS; MOS DEVICES; TRANSISTORS;

FAILURE MODES;

EID: 37549010759     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2007.22     Document Type: Conference Paper

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