Trifecta: A nonspeculative scheme to exploit common, data-dependent subcritical paths

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 1, 2010, Pages 53-65

  Ndai, Patrick ^a   Rafique, Nauman ^b   Thottethodi, Mithuna ^a   Ghosh, Swaroop ^a   Bhunia, Swarup ^c   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

^b GOOGLE INC   (United States)

^c CASE WESTERN RESERVE UNIVERSITY   (United States)

Author keywords

Architecture; Speculative; Variation

Indexed keywords

CRITICAL PATHS; CYCLE OPERATION; DELAY-SLACK; INSTRUCTIONS PER CYCLES; OUT OF ORDER; PIPELINED PROCESSOR; PROCESS VARIATION; SINGLE CYCLE; SINGLE-CLOCK-CYCLE; SUPERSCALAR;

PIPELINES;

PIPELINE PROCESSING SYSTEMS;

EID: 73249132776     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2007491     Document Type: Article

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