Advanced high-κ dielectric stacks with polySi and metal gates: Recent progress and current challenges

IBM Journal of Research and Development

Volumn 50, Issue 4-5, 2006, Pages 387-410

  Gusev, Evgeni P ^a   Narayanan, Vijay ^b   Frank, Martin M ^b  

^a QUALCOMM INC   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRYSTAL DEFECTS; DIELECTRIC MATERIALS; GATES (TRANSISTOR); POLYSILICON; SEMICONDUCTOR DOPING; ULTRATHIN FILMS; WSI CIRCUITS;

DIELECTRIC STACKS; DUAL-WORKFUNCTION METAL-GATE TECHNOLOGY; FULLY SILICIDED GATES;

CMOS INTEGRATED CIRCUITS;

EID: 33748614600     PISSN: 00188646     EISSN: 00188646     Source Type: Journal    
DOI: 10.1147/rd.504.0387     Document Type: Review

References (145)

1. D. Buchanan, "Scaling the Gate Dielectric: Materials, Integration, and Reliability," IBM J. Res. & Dev. 43, No. 3, 245-264 (1999).
2. L. Feldman, E. P. Gusev, and E. Garfunkel, "Ultrathin Dielectrics in Si Microelectronics - An Overview," Fundamental Aspects of Ultrathin Dielectrics on Si-Based Devices, E. Garfunkel, E. P. Gusev, and A. Y. Vul', Eds., Kluwer Academic Publishers, Dordrecht, Netherlands, 1998, p. 1.
3. 2 and Si-O-N Gate Dielectrics Layers for Silicon Microelectronics: Understanding the Processing, Structure and Physical and Electrical Limits," J. Appl. Phys. (Rev). 90, 2057 (2001).
4. P. Balk, "Dielectrics for Field Effect Technology," Adv. Mater. 7, 703 (1995).
5. 2 and Related Dielectrics: Science and Technology, G. Pacchioni, Ed., Kluwer, Dordrecht, Netherlands, 2000, pp. 557-579.
6. N. F. Mott, S. Rigo, F. Rochet, and A. M. Stoneham, "Oxidation of Silicon," Phil. Mag. B 60, 189 (1989).
7. G. D. Wilk, R. M. Wallace, and J. M. Anthony, "High-κ Gate Dielectrics: Current Status and Materials Properties Considerations," J. Appl. Phys. 89, 5243 (2001).
8. High Dielectric Constant Materials: VLSI MOSFET Applications, H. R. Huff and D. C. Gilmer, Eds., Springer, New York, 2004.
9. High-k Gate Dielectrics, M. Houssa, Ed., Taylor and Francis, New York, 2003.
10. Defects in High-κ Dielectrics, E. P. Gusev, Ed., Springer, New York, 2006.
11. A. Callegari, E. Cartier, M. Gribelyuk, H. F. Okorn-Schmidt, and T. Zabel, "Physical and Electrical Characterization of Hafnium Oxide and Hafnium Silicate Sputtered Films," J. Appl. Phys. 90, 6466 (2001).
12. D. C. Gilmer, R. Hegde, R. Cotton, J. Smith, L. Dip, R. Garcia, V. Dhandapani, D. Triyoso, D. Roan, A. Franke, R. Rai, L. Prabhu, C. Hobbs, J. M. Grant, L. La, S. Samavedam, B. Taylor, H. Tseng, and P. Tobin, "Compatibility of Silicon Gates with Hafnium-Based Gate Dielectrics," Microelectron. Eng. 69, 138 (2003).
13. L. Kang, B. H. Lee, W.-J. Qi, Y. Jeon, R. Nieh, S. Gopalan, K. Onishi, and J. C. Lee, "Electrical Characterization of Highly Reliable Ultrathin Hafnium Oxide Gate Dielectric," IEEE Electron Device Lett. 21, 181 (2000).
14. E. P. Gusev, D. A. Buchanan, E. Cartier, A. Kumar, D. DiMaria, S. Guha, A. Callegari, S. Zafar, P. C. Jamison, D. Neumayer, M. Copel, M. A. Gribelyuk, H. Okorn-Schmidt, C. D'Emic, P. Kozlowski, K. Chan, N. Bojarczuk, L. Ragnarsson, P. Ronshein, K. Rim, R. J. Fleming, A. Mocuta, and A. Ajmera, "Ultrathin High-κ Gate Stacks for Advanced CMOS Devices," IEDM Tech. Digest, p. 451 (2001).
15. B. H. Lee, L. Kang, W.-J. Qi, R. Nieh, Y. Jeon, K. Onishi, and J. C. Lee, "Ultrathin Hafnium Oxide with Low Leakage and Excellent Reliability for Alternative Gate Dielectric Application," IEDM Tech. Digest, pp. 133-136 (1999).
16. B. H. Lee, L. Kang, R. Nieh, W.-J. Qi, and J. C. Lee, "Thermal Stability and Electrical Characteristics of Ultrathin Hafnium Oxide Gate Dielectric Reoxidized with Rapid Thermal Annealing," Appl. Phys. Lett. 76, 1926 (2000).
17. G. D. Wilk, R. M. Wallace, and J. M. Anthony, "Hafnium and Zirconium Silicates for Advanced Gate Dielectrics," J. Appl. Phys. 87, 484 (2000).
18. W. J. Zhu, T. P. Ma, S. Zafar, and T. Tamagawa, "Charge Trapping in Ultrathin Hafnium Oxide," IEEE Electron Device Lett. 23, 597 (2002).
19. 3 Post-Deposition Anneal," Appl. Phys. Lett. 82, 1757 (2003).
20. L. Miotti, K. P. Bastos, G. V. Soares, C. Driemeier, R. P. Pezzi, J. Morais, I. J. R. Baumvol, A. L. P. Rotondaro, M. R. Visokay, J. J. Chambers, M. Quevedo-Lopez, and L. Colombo, "Exchange-Diffusion Reactions in HfSiON During Annealing Studied by RBS, NRA and NRRP," Appl. Phys. Lett. 85, 4460 (2004).
21. K. Takahashi, K. Manabe, T. Ikarashi, N. Ikarashi, T. Hase, T. Yoshihara, H. Watanabe, T. Tatsumi, and Y. Mochizuki, "Dual Workfunction Ni-Silicide/HfSiON Gate Stacks by Phase-Controlled Full-Silicidation (PC-FUSI) Technique for 45nm-Node LSTP and LOP Devices," IEDM Tech. Digest, pp. 91-94 (2004).
22. M. R. Visokay, J. J. Chambers, A. L. P. Rotondaro, A. Shanware, and L. Colombo, "Application of HfSiON as a Gate Dielectric Material," Appl. Phys. Lett. 80, 3183 (2002).
23. 2 Films Grown on Silicon by Atomic Layer Deposition for Advanced Gate Dielectrics Applications," Microelectron. Eng. 69, 145 (2003).
24. S. Zafar, A. Kumar, E. P. Gusev, and E. Cartier, "Threshold Voltage Instabilities in High-κ Gate Dielectric Stacks," IEEE Trans. Device & Mater. Reliabil. 5, 45 (2005).
25. 2 Based Gate Dielectric Stacks," J. Appl. Phys. 92, 1232 (2002).
26. M. Copel, M. Gribelyuk, and E. P. Gusev, "Structure and Stability of Ultrathin Zirconium Oxide Films on Silicon," Appl. Phys. Lett. 76, 436 (2000).
27. 3 Dielectrics on Si: Interfacial Metal Diffusion and Mobility Degradation," Appl. Phys. Lett. 81, 2956 (2002).
28. 2 Binary Oxides Deposited by Chemical Solution Deposition," J. Appl. Phys. 90, 1801-1808 (2001).
29. 2 on the Physical and Electrical Properties of the Dielectrics," IEEE Electron Device Lett. 23, 649-651 (2002).
30. 2 Films Grown on Silicon by Atomic Layer Deposition for Advanced Gate Dielectrics Applications," Microelectron. Eng. 69, 145-151 (2003).
31. 2/Si System," Silicon Nitride and Silicon Dioxide Thin Insulating Films and Other Emerging Dielectrics VIII, R. E. Sah, M. J. Deen, J. Zhang, J. Yota, and Y. Kamakura, Eds., PV 2005-01, Electrochemical Society, Piscataway, NJ, 2005, p. 471.
32. S. Guha, E. P. Gusev, M. Copel, L.-Å. Ragnarsson, and D. A. Buchanan, "Compatibility Challenges for High-κ Materials Integration into CMOS Technology," Mater. Res. Soc. Bull. 27, 226-229 (2002).
33. International Technology Roadmap for Semiconductors: 2004 update; see http://public.itrs.net/.
34. G. Lucovsky, C. C. Fulton, Y. Zhang, Y. Zou, J. Luning, L. F. Edge, J. L. Whitten, R. J. Nemanich, H. Ade, D. G. Schlom, V. V. Afanase'v, A. Stesmans, S. Zollner, D. Triyoso, and B. R. Rogers, "Conduction Band-Edge States Associated with the Removal of d-State Degeneracies by the Jahn-Teller Effect," IEEE Trans. Device & Mater. Reliabil. 5, 65-83 (2005).
35. N. V. Nguyen, M. M. Frank, A. V. Davydov, and D. Chandler-Horowitz, "Sub-Bandgap Defect States in Polycrystalline Hafnium Oxide and Their Suppression by Admixture of Silicon," Appl. Phys. Lett. 87, 192903 (2005).
36. 2 Gate Dielectric Stacks," Appl. Phys. Lett. 80, 1975-1977 (2002).
37. 3 Using Atomic Layer Deposition," Appl. Phys. Lett. 81, 4218-4220 (2002).
38. S. H. Bae, C. H. Lee, R. Clark, and D. L. Kwong, "MOS Characteristics of Ultrathin CVD HfAlO Gate Dielectrics," IEEE Electron Device Lett. 24, 556-558 (2003).
39. K. Sekine, S. Inumiya, M. Sato, A. Kaneko, K. Eguchi, and Y. Tsunashima, "Nitrogen Profile Control by Plasma Nitridation Technique for Poly-Si Gate HfSiON CMOSFET with Excellent Interface Property and Ultra-Low Leakage Current," IEDM Tech. Digest, pp. 102-106 (2003).
40. 2 Nanocrystal Memory Using Spinodal Phase Separation of Hafnium Silicate," IEDM Tech. Digest, pp. 1080-1082 (2004).
41. M. A. Quevedo-Lopez, M. R. Visokay, J. J. Chambers, M. J. Bevan, A. LiFatou, L. Colombo, M. J. Kim, B. E. Gnade, and R. M. Wallace, "Dopant Penetration Studies Through Hf Silicate," J. Appl. Phys. 97, 043508 (2005).
42. 2 or Si-O-N) Underlayers," J. Appl. Phys. 92, 7168-7174 (2002).
43. Handbook of Semiconductor Wafer Cleaning Technology: Science, Technology, and Applications, W. Kern, Ed., Noyes Publications, Park Ridge, NJ, 1993.
44. M. M. Frank and Y. J. Chabal, "Mechanistic Studies of Dielectric Growth on Silicon," Materials Fundamentals of Gate Dielectrics, A. Demkov and A. Navrotsky, Eds., Springer, Dordrecht, Netherlands, 2005, pp. 367-401.
45. M. M. Frank, Y. J. Chabal, M. L. Green, A. Delabie, B. Brijs, G. D. Wilk, M.-Y. Ho, E. B. O. da Rosa, I. J. R. Baumvol, and F. C. Stedile, "Enhanced Initial Growth of Atomic-Layer-Deposited Metal Oxides on Hydrogen-Terminated Silicon," Appl. Phys. Lett. 83, 740-742 (2003).
46. R. L. Puurunen, W. Vandervorst, W. F. A. Besling, O. Richard, H. Bender, T. Conard, C. Zhao, A. Delabie, M. Caymax, S. D. Gendt, M. Heyns, M. M. Viitanen, M. D. Ridder, H. H. Brongersma, Y. Tamminga, T. Dao, T. D. Win, M. Verheijen, M. Kaiser, and M. Tuominen, "Island Growth in the Atomic Layer Deposition of Zirconium Oxide and Aluminum Oxide on Hydrogen-Terminated Silicon: Growth Mode Modeling and Transmission Electron Microscopy," J. Appl. Phys. 96, 4878-4889 (2004).
47. 3 as the Oxidant," J. Appl. Phys. 94, 3641-3647 (2003).
48. 3 Oxidation," J. Appl. Phys. 96, 2323 (2004).
49. M. M. Frank, Y. J. Chabal, and G. D. Wilk, "Nucleation and Interface Formation Mechanisms in Atomic Layer Deposition of Gate Oxides," Appl. Phys. Lett. 82, 4758-4760 (2003).
50. M.-T. Ho, Y. Wang, R. T. Brewer, L. S. Wielunski, Y. J. Chabal, N. Moumen, and M. Boleslawski, "In Situ Infrared Spectroscopy of Hafnium Oxide Growth on Hydrogen-Terminated Silicon Surfaces by Atomic Layer Deposition," Appl. Phys. Lett. 87, 133103 (2005).
51. S. Rivillon, F. Amy, Y. J. Chabal, and M. M. Frank, "Gas Phase Chlorination of Hydrogen-Passivated Silicon Surfaces," Appl. Phys. Lett. 85, 2583 (2004).
52. C. C. Finstad and A. J. Muscat, "Atomic Layer Deposition of Silicon Nitride Barrier Layer for Self-Aligned Gate Stack," Proceedings of the 8th International Symposium on Cleaning Technology in Semiconductor Device Manufacturing, J. Ruzyllo, T. Hattori, R. Opila, and R. E. Novak, Eds., PV 2003-26, Electrochemical Society, Piscataway, NJ, 2004, p. 86.
53. M. M. Frank, H. Shang, S. Rivillon, F. Amy, C.-L. Hsueh, V. K. Paruchuri, R. T. Mo, M. Copel, E. P. Gusev, M. A. Gribelyuk, and Y. J. Chabal, "High-κ Gate Dielectrics on Silicon and Germanium: Impact of Surface Preparation," Solid State Phenom. 103-104, 3-6 (2005).
54. 3," Rapid Thermal and Other Short-Time Processing Techniques, F. Rooseboom, P. Timans, K. G. Reid, M. C. Ozturk, D. L. Kwong, and E. P. Gusev, Eds., Electrochemical Society, Pennington, NJ, 2001, p. 189.
55. R. T. Brewer, M.-T. Ho, K. Z. Zhang, L. V. Goncharova, D. G. Starodub, T. Gustafsson, Y. J. Chabal, and N. Moumen, "Ammonia Pretreatment for High-κ Dielectric Growth on Silicon," Appl. Phys. Lett. 85, 3830-3832 (2004).
56. X. Shi, M. Shriver, Z. Zhang, T. Higman, and S. A. Campbell, "Properties of High-κ/Ultrahigh Purity Silicon Nitride Stacks," J. Vac. Sci. Technol. A 22, 1146-1151 (2004).
57. M. M. Frank, K. Maitra, E. A. Cartier, B. P. Linder, P. C. Jamison, M. S. Gordon, and M. Copel, "Nitrogen in Poly-Si/HfSiO Gate Stacks: Carrier Mobility Impact of Traps and Fixed Charge," presented at the 36th IEEE Semiconductor Interface Specialists Conference (SISC), Arlington, VA, 2005.
58. M. V. Fischetti, D. A. Neumayer, and E. A. Cartier, "Effective Electron Mobility in Si Inversion Layers in Metal-Oxide-Semiconductor Systems with a High-Kappa Insulator: The Role of Remote Phonon Scattering," J. Appl. Phys. 90, 4587-4608 (2001).
59. Z. Ren, M. Fischetti, E. P. Gusev, E. Cartier, and M. Chudzik, "Inversion Channel Mobility in High-κ High Performance MOSFETs," Symp. VLSI Technol., p. 793 (2003).
60. M. M. Frank, V. K. Paruchuri, V. Narayanan, N. Bojarczuk, B. Linder, S. Zafar, E. A. Cartier, E. P. Gusev, P. C. Jamison, K.-L. Lee, M. L. Steen, M. Copel, S. A. Cohen, K. Maitra, X. Wang, P. M. Kozlowski, J. S. Newbury, D. R. Medeiros, P. Oldiges, S. Guha, R. Jammy, M. Ieong, and G. Shahidi, "Poly-Si/High-κ Gate Stacks with Near-Ideal Threshold Voltage and Mobility," IEEE VLSI-TSA-Tech, International Symposium on VLSI Technology, 2005, pp. 97-98.
61. J. Koomen, "Investigation of the MOST Channel Conductance in Weak Inversion," Solid-State Electron. 16, 801-810 (1973).
62. C. G. Sodini, T. W. Ekstedt, and J. L. Moll, "Charge Accumulation and Mobility in Thin Dielectric MOS Transistors," Solid-State Electron. 25, 833-841 (1982).
63. T. Hori, "Inversion Layer Mobility Under High Normal Field in Nitrided-Oxide Mosfets," IEEE Trans. Electron Devices 37, 2058-2069 (1990).
64. E. P. Gusev, H.-C. Lu, E. L. Garfunkel, T. Gustafsson, and M. L. Green, "Growth and Characterization of Ultrathin Nitrided Silicon Oxide Films," IBM J. Res. & Dev. 43, No. 3, 265-286 (1999).
65. E. P. Gusev, D. A. Buchanan, P. Jamison, T. H. Zabel, and M. Copel, "Ultrathin Nitrided Gate Dielectrics by Plasma-Assisted Processing," Microelectron. Eng. 48, 67 (1999).
66. E. P. Gusev, E. Cartier, D. A. Buchanan, M. A. Gribelyuk, M. Copel, H. Okorn-Schmidt, and C. D'Emic, "Ultrathin High-κ Metal Oxides on Silicon: Processing, Characterization and Integration Issues," Microelectron. Eng. 59, 341 (2001).
67. C. Hobbs, L. Fonseca, V. Dhandapani, S. Samavedam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hegde, D. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R. Rai, L. Hebert, H. Tseng, B. White, and P. Tobin, "Fermi Level Pinning at the Poly-Si/Metal Oxide Interface," Symp. VLSI Technol., p. 9 (2003).
68. C. C. Hobbs, L. R. C. Fonseca, A. Knizhnik, V. Dhandapani, S. B. Samavedam, W. J. Taylor, J. M. Grant, L. G. Dip, D. H. Triyoso, R. I. Hegde, D. C. Gilmer, R. Garcia, D. Roan, M. L. Lovejoy, R. S. Rai, E. A. Hebert, H. H. Tseng, S. G. H. Anderson, B. E. White, and P. J. Tobin, "Fermi-Level Pinning at the Polysilicon Metal Oxide Interface - Part II," IEEE Trans. Electron Devices 51, 978-984 (2004).
69. C. C. Hobbs, L. R. C. Fonseca, A. Knizhnik, V. Dhandapani, S. B. Samavedam, W. J. Taylor, J. M. Grant, L. G. Dip, D. H. Triyoso, R. I. Hegde, D. C. Gilmer, R. Garcia, D. Roan, M. L. Lovejoy, R. S. Rai, E. A. Hebert, H. H. Tseng, S. G. H. Anderson, B. E. White, and P. J. Tobin, "Fermi-Level Pinning at the Polysilicon/Metal Oxide Interface - Part I," IEEE Trans. Electron Devices 51, 971-977 (2004).
70. t with Hf-Based Gate Stacks with Poly-Si and FUSI Gates," Symp. VLSI Technol., p. 44 (2004).
71. M. Miyamura, K. Masuzaki, H. Watanabe, N. Ikarashi, and T. Tatsumi, "Origin of Flatband Voltage Shift in Poly-Si/Hf-Based High-κ Gate Dielectrics and Flatband Voltage Dependence on Gate Stack Structure," Jpn. J. Appl. Phys. Part 1 43, 7843-7847 (2004).
72. fb-Shift Problem of Hf/Polysilicon-Based Gate Stacks: A Solution-Based Survey," Microelectron. Reliabil. 45, 786-789 (2005).
73. V. Kaushik, E. Rohr, S. Hyun, S. D. Gendt, S. V. Elshocht, A. Delabie, J.-L. Everaert, A. Veloso, S. Brus, L. Ragnarsson, O. Richard, M. Caymax, and M. Heyns, "Threshold Voltage Control in PMOSFETs with Polysilicon or Fully-Silicided Gates on Hf-Based Gate Dielectric Using Controlled Lateral Oxidation," Proceedings of the Conference on High Dielectric Constant Gate Stacks III, S. Kar, D. Misra, H. Iwai, M. Houssa, D. Landheer, W. Tsai, S. De Gendt, and A. Chin, Eds., Electrochemical Society, NJ, in press.
74. H. Takeuchi, H. Y. Wong, D. Ha, and T.-J. King, "Impact of Oxygen Vacancies on High-κ Gate Stack Engineering," IEDM Tech. Digest, pp. 829-832 (2004).
75. 2," Symp. VLSI Technol., p. 230 (2005).
76. W. E. Spicer, Z. Liliental-Weber, E. Weber, N. Newman, T. Kendelewicz, R. Cao, C. McCants, P. Mahowald, K. Miyano, and I. Lindau, "The Advanced Unified Defect Model for Schottky Barrier Formation," J. Vac. Sci. Technol. B 6, 1245 (1988).
77. 3 Gate Dielectrics on GaAs Grown by Atomic Layer Deposition," Appl. Phys. Lett. 86, 152904 (2005).
78. +poly-Si Gates - A Theoretical Approach," Jpn. J. Appl. Phys. 43, L1413-L1415 (2004).
79. K. Shiraishi, K. Yamada, K. Torii, Y. Akasaka, K. Nakajima, M. Kohno, T. Chikyo, H. Kitajima, and T. Arikado, "Physics in Fermi Level Pinning at the PolySi/Hf-Based High-κ Oxide Interface," Symp. VLSI Technol., p. 108 (2004).
80. 2 and In-Situ Metal-Oxynitride Gate Stack," Proceedings of the International Workshop on Dielectric Thin Films for Future ULSI Devices, 2004, p. 11.
81. H.-S. Jung, J.-H. Lee, S. K. Han, Y.-S. Kim, H. J. Lim, M. J. Kim, S. J. Doh, M. Y. Yu, N.-I. Lee, H.-L. Lee, T.-S. Jeon, H.-J. Cho, S. B. Kang, S. Y. Kim, I. S. Park, D. Kim, H. S. Baik, and Y. S. Chung, "A Highly Manufacturable MIPS (Metal Inserted Poly-Si Stack) Technology with Novel Threshold Voltage Control," Symp. VLSI Technol., pp. 232-233 (2005).
82. W. S. Kim, S. Kamiyama, T. Aoyama, H. Itoh, T. Maeda, T. Kawahara, K. Torii, H. Kitajima, and T. Arikado, "Depletion-Free Poly-Si Gate High-κ CMOSFETs," IEDM Tech. Digest, pp. 833-836 (2004).
83. 3 Capping Layer on pMOS," IEEE Electron Device Lett. 26, 441-444 (2005).
84. 3 Capped Hf-Silicate Gate Stacks," Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment, E. P. Gusev, L. J. Chen, D.-L. Kwong, P. J. Timans, F. Roozeboom, M. C. Öztürk, and H. Iwai, Eds., PV 2005-05, Electrochemical Society, Pennington, NJ, 2005, pp. 118-124.
85. K. L. Lee, M. M. Frank, V. Paruchuri, E. Cartier, B. Linder, N. Bojarczuk, X. Wang, J. Rubino, M. Steen, P. Kozlowski, J. Newbury, E. Sikorski, P. Flaitz, M. Gribelyuk, P. Jamison, G. Singco, V. Narayanan, S. Zafar, S. Guha, P. Oldiges, R. Jammy, and M. Ieong, "Poly-Si/AIN/ HfSiO Stack for Ideal Threshold Voltage and Mobility in Sub-100 nm MOSFETs," Symp. VLSI Technol., pp. 202-203 (2006).
86. C. Cabral, Jr., C. Lavoie, A. S. Ozcan, R. S. Amos, V. Narayanan, E. P. Gusev, J. L. Jordan-Sweet, and J. M. E. Harper, "Evaluation of Thermal Stability for CMOS Gate Metal Materials," J. Electrochem Soc. 151, F283 (2004).
87. 2 Gate Dielectric," IEDM Tech. Digest, p. 433 (2002).
88. 2 Based Gate Dielectrics for High Performance Logic Applications," Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials, 2003, p. 730.
89. 2 MISFETs with Sub-1 nm EOT," Symp. VLSI Technol., p. 228 (2005).
90. Z. Q. Chen, V. Misra, R. P. Haggerty, and S. Stemmer, "Stability of Ru- and Ta-Based Metal Gate Electrodes in Contact with Dielectrics for Si-CMOS," Phys. Stat. Solidi 241, 2253 (2004).
91. 2 nMOS and pMOSFETs," IEDM Tech. Digest, p. 311 (2003).
92. J. K. Schaeffer, L. R. C. Fonseca, S. B. Samavedam, Y. Liang, P. J. Tobin, and B. E. White, "Contributions to the Effective Work Function of Platinum on Hafnium Dioxide," Appl. Phys. Lett. 85, 1826-1828 (2004).
93. 2 Gate Stacks," IEDM Tech. Digest, p. 825 (2004).
94. V. Narayanan, A. Callegari, F. R. McFeely, K. Nakamura, P. Jamison, S. Zafar, E. Cartier, A. Steegen, V. Ku, P. Nguyen, K. Milkove, C. J. Cabral, M. Gribelyuk, C. Wajda, Y. Kawano, D. Lacey, Y. Li, E. Sikorski, F. Duch, H. Ng, C. Wann, R. Jammy, M. Ieong, and G. Shahidi, "Dual Work Function Metal Gate CMOS Using CVD Metal Electrodes," Symp. VLSI Technol., p. 192 (2004).
95. M. Fischetti, D. Neumayer, and E. Cartier, "Effective Electron Mobility in Si Inversion Layers in MOS Systems with a High-k Insulator: The Role of Remote Phonon Scattering," J. Appl. Phys. 90, 4587 (2001).
96. 2 Dielectrics," Appl. Phys. Lett. 85, 672-674 (2004).
97. 2/Si (001) films," Appl. Phys. Lett. 85, 458-460 (2004).
98. G. Bersuker, J. Peterson, J. Barnett, A. Korkin, J. H. Sim, R. Choi, B. H. Lee, J. Greer, P. Lysaght, and H. R. Huff, "Properties of the Interfacial Layer in the High-k Gate Stack and Transistor Performance," Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment, E. P. Gusev, L. J. Chen, H. Iwai, D. L. Kwong, M. Ozturk, F. Roozeboom, and P. Timans, Eds., PV 2005-05, Electrochemical Society, Piscataway, NJ, 2005, p. 141.
99. 2/TaN Low Thermal-Budget n-Channel FETs with Solid-Phase Epitaxially Regrown (SPER) Junctions," Symp. VLSI Technol., p. 234 (2005).
100. K. Maitra, "Electron Transport in Bulk-Si NMOSFETs in Presence of High-κ Gate Insulator - Charge Trapping and Mobility," Ph.D. Dissertation, North Carolina State University, Raleigh, 2005.
101. G. Lucovsky and J. C. Philips, "Bond Strain and Interfaces in High-κ Gate Stacks," Microelectron. Reliabil. 45, 770 (2005).
102. 2/Metal Stacks," IEEE Electron Device Lett. (2006), in press.
103. R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros, and M. Metz, "High-κ Metal-Gate Stack and Its MOSFET Characteristics," IEEE Electron Device Lett. 25, 408 (2004).
104. P. D. Kirsch, J. H. Sim, S. C. Song, S. Krishnan, J. Peterson, H.-J. Li, M. Quevedo-Lopez, C. D. Young, R. Choi, N. Moumen, P. Majhi, Q. Wang, J. G. Ekerdt, G. Bersuker, and B. H. Lee, "Mobility Enhancement of High-k Gate Stacks Through Reduced Transient Charging," Proceedings of the 35th European Solid-State Device Research Conference, Grenoble, France, 2005, p. 367.
105. 2 Gated Silicon Field-Effect Transistors," J. Appl. Phys. 85, 6230 (2004).
106. 2/Si Structures by Fowler-Nordheim Current Analysis," Appl. Phys. Lett. 80, 1403 (2002).
107. R. G. Wilson, "Vacuum Thermionic Work Functions of Polycrystalline Nb, Mo, Ta, Re, Os, Ir," J. Appl. Phys. 37, 3170 (1966).
108. 2/Metal Stacks: Determination of Energy Level Diagram, Work Functions and Their Dependence on Metal Deposition," Symp. VLSI Technol., p. 44 (2005).
109. C. Hobbs, L. Fonseca, V. Dhandapani, S. Samavedam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hedge, D. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R. Rai, L. Hebert, H. Tseng, B. White, and P. Tobin, "Fermi-Level Pinning at the PolySi/Metal Oxide Interface," Symp. VLSI Technol., p. 9 (2003).
110. 2 High-κ Gate Oxide," Microelectron. Eng. 80, 408 (2005).
111. Y. C. Yeo, T. J. King, and C. M. Hu, "Metal-Dielectric Band Alignment and Its Implications for Metal Gate Complementary Metal-Oxide-Semiconductor Technology," J. Appl. Phys. 92, 7266-7271 (2002).
112. D. Lim, R. Haight, M. Copel, and E. Cartier, "Oxygen Defects and Fermi Level Location in Metal-Hafnium Oxide-Silicon Structures," Appl. Phys. Lett. 87, 072902 (2005).
113. S. Zafar, A. Callegari, E. P. Gusev, and M. V. Fischetti, "Charge Trapping Related Threshold Voltage Instabilities in High Permittivity Gate Dielectric Stacks," J. Appl. Phys. 93, 9298 (2003).
114. 2 High-κ Gate Stacks," Microelectron. Eng. 72, 273 (2004).
115. E. P. Gusev, V. Narayanan, S. Zafar, C. Cabral, Jr., E. Cartier, N. Bojarczuk, A. Callegari, R. Carruthers, M. Chudzik, C. D'Emic, E. Duch, P. Jamison, P. Kozlowski, D. La Tulipe, K. Maitra, F. R. McFeely, J. Newbury, V. Paruchuri, and M. Steen, "Charge Trapping in Aggressively Scaled Metal Gate/High-κ Stacks," IEDM Tech. Digest, p. 729 (2004).
116. 2 Gate-Dielectric Stacks with Tungsten Gates," IEEE Electron Device Lett. 25, 153-155 (2004).
117. S. P. Murarka, "Refractory Silicides for Integrated Circuits," J. Vac. Sci. Technol. 17, 775 (1980).
118. S. P. Murarka, D. B. Fraser, A. Sinha, and H. J. Levinstein, "Refractory Silicides of Ti and Ta for Low-Resistivity Gates and Interconnects," IEEE Trans. Electron Devices 27, 1409 (1980).
119. S. Inoue, N. Toyokura, T. Nakamura, and H. Ishikawa, "Phosphorus-Doped Molybdenum Silicide Films for LSI Applications," J. Electrochem. Soc. 128, 2402 (1981).
120. 2 Gate MOSFET," IEEE Trans. Electron Devices 27, 1431 (1980).
121. M. Qin, V. M. C. Poon, and S. C. H. Ho, "Investigation of Polycrystalline Nickel Silicide Films as Gate Materials," J. Electrochem. Soc. 148, G271 (2001).
122. K. Roh, S. Youn, S. Yang, and Y. Roh, "Tungsten Silicide for Alternate Gate Metal in MOS Devices," J. Vac. Sci. Technol. A 19, 1562 (2001).
123. 2) Polysilicon: A Novel Approach to Very-Low-Resistive Gate Without Metal CMP nor Etching," IEDM Tech. Digest, p. 3751 (2001).
124. Z. Krivokapic, W. P. Maszara, K. Achutan, P. King, J. Gray, M. Sidorow, E. Zhao, J. Zhang, J. Chan, A. Marathe, and M. R. Lin, "Nickel Silicide Metal Gate FDSOI Devices with Improved Oxide Leakage," IEDM Tech. Digest, p. 271 (2002).
125. W. P. Maszara, Z. Krivokapic, P. King, J. S. Goo, and M. R. Lin, "Transistors with Dual Work Function Metal Gates by Single Full Silicidation (FUSI) of Polysilicon," IEDM Tech. Digest, p. 367 (2002).
126. J. Kedzierski, D. Boyd, P. Ronsheim, S. Zafar, J. Newbury, J. Ott, C. Cabral, M. Ieong, and W. Haensch, "Threshold Voltage Control in NiSi-Gated MOSFETs Through Silicidation Induced Impurity Segregation," IEDM Tech. Digest, p. 1331 (2003).
127. J. Kedzierski, D. Boyd, Y. Zhang, M. Steen, F. F. Jamin, J. Benedict, M. Ieong, and W. Haensch, "Issues in NiSi-Gated FDSOI Device Integration," IEDM Tech. Digest, p. 1841 (2003).
128. 3 MOSFETs," IEEE Electron Device Lett. 24, 348 (2003).
129. D. Aime, B. Froment, F. Cacho, V. Carron, S. Descombes, Y. Morand, N. Emonet, F. Wacquant, T. Farjot, S. Jullian, C. Laviron, M. Juhel, R. Pantel, R. Molins, D. Delille, A, Halimaoui, and D. Bensahel, "Work Function Tuning Through Dopant Scanning and Related Effects in Ni Fully Silicided Gate for Sub-45 nm Nodes CMOS," IEDM Tech. Digest, pp. 87-90 (2004).
130. 2 Based High-κ Gate Dielectrics as a Candidate for
131. E. P. Gusev, C. Cabral, B. P. Linder, Y. H. Kim, K. Maitra, E. Cartier, H. Nayfeh, R. Amos, G. Biery, N. Bojarczuk, A. Callegari, R. Carruthers, S. A. Cohen, M. Copel, S. Fang, M. Frank, S. Guha, M. Gribelyuk, P. Jamison, R. Jammy, M. Ieong, J. Kedzierski, P. Kozlowski, V. Ku, D. Lacey, D. La Tulipe, V. Narayanan, H. Ng, P. Nguyen, J. Newbury, V. Paruchuri, R. Rengarajan, G. Shahidi, A. Steegen, M. Steen, S. Zafar, and Y. Zhang, "Advanced Gate Stacks with Fully Silicided (FUSI) Gates and High-κ Dielectrics: Enhanced Performance at Reduced Gate Leakage," IEDM Tech. Digest, pp. 79-82 (2004).
132. W. Maszara, "Fully Silicided Metal Gates for High Performance CMOS Technology," Advanced Short-Time Thermal Processing for Si-Based CMOS Devices II, E. P. Gusev, F. Roozeboom, P. Timans, M. Ozturk, L. Chen, and G. Miner, Eds., Electrochemical Society, Pennington, NJ, 2004.
133. T. Nabatame, M. Kadoshima, K. Iwamoto, N. Mise, S. Magita, M. Ohno, H. Ota, N. Yasuda, A. Ogawa, K. Tominaga, H. Satake, and A. Toriumi, "Partial Silicides Technology for Tunable Work Function Electrodes on High-κ Dielectrics," IEDM Tech. Digest, p. 421 (2004).
134. C. S. Park, B. J. Cho, and D. L. Kwong, "Thermally Stable Fully Silicided Hf-Silicide Metal Gate Electrode," IEEE Electron Device Lett. 25, 610 (2004).
135. J. H. Sim, H. C. Wen, J. P. Lu, and D. L. Kwong,"Work Function Tuning of Fully Silicided NiSi Metal Gates Using a TiN Capping Layer," IEEE Electron Device Lett. 25, 610 (2004).
136. P. Xuan and J. Bokor, "Investigation of NiSi and TiSi as CMOS Gate Material," IEEE Electron Device Lett. 24, 634 (2004).
137. 3-Ge-on-Insulator n- and p-MOSFETs with Fully NiSi and NiGe Dual Gates," IEEE Electron Device Lett. 25, 138 (2004).
138. N. Biswas, J. Gurganus, V. Misra, Y. Yang, and S. Stemmer, "Evaluation of Ni and Mo Silicides for Dual Gate CMOS Applications," Appl. Phys. Lett. 86, 22105 (2005).
139. C. Y. Kang, P. Lasaght, R. Choi, B. H. Lee, S. J. Rhee, C. H. Choi, M. S. Akbar, and J. C. Lee, "Nickel-Silicide Phase Effects on Flatband Voltage Shift and Equivalent Oxide Thickness Decrease of Hafnium Silicon Oxynitride MOS Capacitors," Appl. Phys. Lett. 86, 222906 (2005).
140. Y. H. Kim, C. Cabral, E. P. Gusev, R. Carruthers, L. Gignac, M. Gribelyuk, E. Cartier, V. Narayanan, J. Newbury, B. Price, J. Acevedo, P. Jamison, B. Linder, W. Natzle, J. Cai, R. Jammy, and M. Ieong, "Systematic Study of Workfunction Engineering Using NiSi Alloy FUSI Metal Gates with Advanced Gate Stacks," IEDM Tech. Digest (2005).
141. 2 and NiSi Fully Silicided Metal Gates," Electrochem. & Solid-State Lett. 8, G119 (2005).
142. H. C. Wen, J. H. Sim, J. P. Lu, and D. L. Kwong, "Effect of Ni Thickness Dependence on NiSi FUSI Metal Gate Characteristics," Electrochem. & Solid-State Lett. 7, G258 (2005).
143. Y. Lebedinskii, A. Zenkevich, and E. P. Gusev, "Monitoring of Fermi Level Variations at Metal/High-κ Interfaces with In Situ X-Ray Photoelectron Spectroscopy," Defects in High-k Dielectric Stacks, E. P. Gusev, Ed., Springer, New York, 2006, p. 339.
144. M. Niwa, R. Mitsuhashi, K. Yamamoto, S. Hayashi, A. Rothchild, S. Kubicek, S. D. Gendt, and S. Biesemans, "PVD-High-κ Gate Dielectrics with FUSI Gate and Influence of PDA Treatment on On-State Drive Current," Defects in High-k Dielectric Stacks, E. P. Gusev, Ed., Springer, New York, 2006, p. 1.
145. K. S. Krisch, J. D. Bude, and L. Manchanda, "Gate Capacitance Attenuation in MOS Devices with Thin Gate Dielectrics," IEEE Electron Device Lett. 17, 521 (1996).